Error Rate Estimation for Defective Circuits via Ones Counting
Article No.: 8, Pages 1 - 14
Abstract
With VLSI circuit feature size scaling down, it is becoming more difficult and expensive to achieve a desired level of yield. Error-tolerance employs defective chips that occasionally produce erroneous yet acceptable results in targeted applications, and has been proposed as one way to increase effective yield. These chips are characterized by criteria set by specific applications. Error rate, an upper-bound on how frequent errors occur at an output, is one such criterion. In this article we focus on the following problem: given a combinational logic circuit that is defective, and hence occasionally produces an erroneous output, how can we determine the error rate of each output line by using ones counting? The results of this work can also be used for runtime error estimation in aging systems and in environments where soft-errors are produced.
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Index Terms
- Error Rate Estimation for Defective Circuits via Ones Counting
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Publication History
Published: 01 January 2012
Accepted: 01 August 2011
Revised: 01 January 2011
Received: 01 July 2009
Published in TODAES Volume 17, Issue 1
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