skip to main content
research-article

Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs

Published: 01 January 2012 Publication History

Abstract

This article re-examines the soft error effect caused by radiation-induced particles beyond the deep submicron regime. Considering the impact of process variations, voltage pulse widths of transient faults are found no longer monotonically diminishing after propagation, as they were formerly. As a result, the soft error rates in scaled electronic designs escape traditional static analysis and are seriously underestimated. In this article we formulate the statistical soft error rate (SSER) problem and present two frameworks to cope with the aforementioned sophisticated issues. The table-lookup framework captures the change of transient-fault distributions implicitly by using a Monte-Carlo approach, whereas the SVR-learning framework does the task explicitly by using statistical learning theory. Experimental results show that both frameworks can more accurately estimate SERs than static approaches do. Meanwhile, the SVR-learning framework outperforms the table-lookup framework in both SER accuracy and runtime.

References

[1]
Amusan, O. A., Massengill, L. W., Bhuva, B. L., DasGupta, S., Witulski, A. F., and Ahlbin, J. R. 2007. Design techniques to reduce set pulse widths in deep-submicron combinational logic. IEEE Trans. Nuclear Sci. 54, 6, 2060--2064.
[2]
Bartlett, W. and Spainhower, L. 2004. Commercial fault tolerance: A tale of two systems. IEEE Trans. Depend. Secure Comput. 1, 1, 87--96.
[3]
Bates, D. M. and Watts, D. G. 1988. Nonlinear Regression Analysis and Its Applications. Wiley.
[4]
Borkar, S., Karnik, T., Narendra, S., Tschanz, J., Keshavarzi, A., and De, V. 2003. Parameter variations and impact on circuits and microarchitecture. In Proceedings of the Design Automation Conference. 338--342.
[5]
Bowman, K., Duvall, S., and Meindl, J. 2002. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. Solid-State Circuits 37, 2, 183--190.
[6]
Brglez, F. and Fujiwara, H. 1985. A neural netlist of ten combinational benchmark circuits and translator in Fortran. In Proceedings of the International Symposium on Circuits and Systems.
[7]
Cha, H. and Patel, J. H. 1993. A logic-level model for particle hits in CMOS circuits. In Proceedings of the International Conference on Circuit Design. 538--542.
[8]
Choi, S. H., Paul, B. C., and Roy, K. 2004. Novel sizing algorithm for yield improvement under process variation in nanometer technology. In Proceedings of the Design Automation Conference. 454--459.
[9]
Cristianini, N. and Shawe-Taylor, J. 2002. An Introduction to Support Vector Machines and Other Kernel-based Learning Methods. Cambridge University Press.
[10]
Dodd, P. E. and Massengill, L. W. 2003. Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans. Nuclear Sci. 50, 3, 583--602.
[11]
Edamatsu, H., Homma, K., Kakimoto, M., Koike, Y., and Tabuchi, K. 1998. Pre-layout delay calculation specification for CMOS ASIC libraries. In Proceedings of the Asian South Pacific Design Automation Conference (ASP-DAC). 241--248.
[12]
Ferlet-Cavrois, V., Paillet, P., McMorrow, D., Fel, N., Baggio, J., Girard, S., Duhamel, O., Melinger, J. S., Gaillardin, M., Schwank, J. R., Dodd, P. E., Shaneyfelt, M. R., and Felix, J. A. 2007. New insights into single event transient propagation in chains of inverters-evidence for propagation-induced pulse broadening. IEEE Trans. Nuclear Sci. 54, 6, 2338--2346.
[13]
Garg, R., Nagpal, C., and Khatri, S. P. 2008. A fast, analytical estimator for the seu-induced pulse width in combinational designs. In Proceedings of the Design Automation Conference. 918--923.
[14]
Krishnaswamy, S., Markov, I., and Hayes, J. P. 2008. On the role of timing masking in reliable logic circuit design. In Proceedings of the Design Automation Conference. 924--929.
[15]
Miskov-Zivanov, N. and Marculescu, D. 2006. Mars-c: Modeling and reduction of soft errors in combinational circuits. In Proceedings of the Design Automation Conference. 767--772.
[16]
Miskov-Zivanov, N., Wu, K.-C., and Marculescu, D. 2008. Process variability-aware transient fault modeling and analysis. In Proceedings of the International Conference on Computer Aided Design. 685--690.
[17]
Mitra, S., Seifert, N., Zhang, M., Shi, Q., and Kim, K. S. 2005. Robust system design with built-in soft error resilience. IEEE Trans. Computer 38, 2, 43--52.
[18]
Mohanram, K. 2005. Closed-form simulation and robustness models for seu-tolerant design. In Proceedings of the VLSI Test Symposium. 327--333.
[19]
Mukherjee, S., Kontz, M., and Reihardt, S. 2002. Detailed design and evaluation of redundant multithreading alternatives. In Proceedings of the International Symposium on Computer Architecture. 99--110.
[20]
Nangate Inc. 2008. Nangate 45nm Open Library. http://www.nangate.com/.
[21]
Nanoscale Integration and Modeling Group. 2008. Predictive Technology Model. Nanoscale Integration and Modeling Group. http://www.eas.asu.edu/ ptm/.
[22]
Natarajan, S., Breuer, M., and Gupta, S. 1998. Process variations and their impact on circuit operation. In Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems. 73--81.
[23]
Omana, M., Papasso, G., Rossi, D., and Metra, C. 2003. A model for transient fault propagation in combinational logic. In Proceedings of the International On-Line Testing Symposium. 111--115.
[24]
Rajaraman, R., Kim, J. S., Vijaykrishnan, N., Xie, Y., and Irwin, M. J. 2006. Seat-la: A soft error analysis tool for combinational logic. In Proceedings of the International Conference on VLSI Design. 499--502.
[25]
Ramakrishnan, K., Rajaraman, R., Suresh, S., Vijaykrishnan, N., Xie, Y., and Irwin, M. J. 2007. Variation impact on ser of combinational circuits. In Proceedings of the International Symposium on Quality Electronic Design. 911--916.
[26]
Rao, R., Chopra, K., Blaauw, D., and Sylvester, D. 2006. An efficient static algorithm for computing the soft error rates of combinational circuits. In Proceedings of the Design Automation and Test in Europe Conference. 164--169.
[27]
Salzmann, J., Sill, F., and Timmermann, D. 2007. Algorithm for fast statistical timing analysis. In Proceedings of the International Symposium on System-on-Chip. 1--4.
[28]
Semiconductor Roadmap Committee of Japan. 2003. Parameters of low power SoC design. http://strj-jeita.elisasp.net/pdf-nenjihou_koku-0303-roadmap/3-13_setsukeitask_force.pdf.
[29]
Shivakumar, P., Kistler, M., Keckler, S. W., Burger, D., and Alvisi, L. 2002. Modeling the effect of technology trends on the soft error rate of combinational logic. In Proceedings of the International Conference on Dependable Systems and Networks. 389--398.
[30]
Smola, A. J., Scholkopf, B., and Olkopf, B. S. 2003. A tutorial on support vector regression. Tech. rep., Statistics and Computing.
[31]
Tosaka, Y., Hanata, H., Itakura, T., and Satoh, S. 1999. Simulation technologies for cosmic ray neutron-induced soft errors: Models and simulation systems. IEEE Trans. Nuclear Sci. 46, 3, 774--780.
[32]
Vapnik, V. N. 1995. The Nature of Statistical Learning Theory. Springer, Berlin.
[33]
Weisberg, S. 2005. Applied Linear Regression 3rd Ed., Wiley.
[34]
Weste, N. H. E. and Harris, D. 2005. CMOS VLSI Design - A Circuit and Systems Perspective 3rd Ed., Addison Wesley, Boston.
[35]
Zhang, B., Wang, W.-S., and Orshansky, M. 2006. Faser: Fast analysis of soft error susceptibility for cell-based designs. In Proceedings of the International Symposium on Quality Electronic Design. 755--760.
[36]
Zhang, M. and Shanbhag, N. 2004. A soft error rate analysis (sera) methodology. In Proceedings of the International Conference on Computer Aided Design. 111--118.
[37]
Zhang, M., Mak, T., Tschanz, J., Kim, K., Seifert, N., and Lu, D. 2007. Design for resilience to soft errors and variations. In Proceedings of the International On-Line Test Symposium. 23--28.

Cited By

View all
  • (2018)A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT.2018.8602855(1-6)Online publication date: Oct-2018
  • (2016)Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults—From Device to Circuit LevelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.247435535:4(586-597)Online publication date: Apr-2016
  • (2016)Statistical soft error rate estimation of combinational circuits using Bayesian networksCOMPEL - The international journal for computation and mathematics in electrical and electronic engineering10.1108/COMPEL-09-2015-031735:5(1760-1773)Online publication date: 5-Sep-2016
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 17, Issue 1
January 2012
224 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/2071356
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

Publication History

Published: 01 January 2012
Accepted: 01 August 2011
Revised: 01 May 2011
Received: 01 June 2010
Published in TODAES Volume 17, Issue 1

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. Monte Carlo method
  2. Soft error
  3. statistical learning
  4. support vector machine
  5. transient fault

Qualifiers

  • Research-article
  • Research
  • Refereed

Funding Sources

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)9
  • Downloads (Last 6 weeks)0
Reflects downloads up to 17 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2018)A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT.2018.8602855(1-6)Online publication date: Oct-2018
  • (2016)Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults—From Device to Circuit LevelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.247435535:4(586-597)Online publication date: Apr-2016
  • (2016)Statistical soft error rate estimation of combinational circuits using Bayesian networksCOMPEL - The international journal for computation and mathematics in electrical and electronic engineering10.1108/COMPEL-09-2015-031735:5(1760-1773)Online publication date: 5-Sep-2016
  • (2016)Parallel SER analysis for combinational and sequential standard cell circuitsMicroelectronics Journal10.1016/j.mejo.2016.01.00750:C(8-19)Online publication date: 1-Apr-2016
  • (2013)Fall Detection by a SVM-Based Cloud System with Motion SensorsAdvanced Technologies, Embedded and Multimedia for Human-centric Computing10.1007/978-94-007-7262-5_5(37-45)Online publication date: 13-Nov-2013
  • (2012)Statistical Analysis of Soft Error Rate in Digital Logic Design Including Process VariationsIEEE Transactions on Nuclear Science10.1109/TNS.2012.221907059:6(2811-2817)Online publication date: Dec-2012

View Options

Login options

Full Access

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media