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Power and area optimisation in heterogeneous 3D networks-on-chip architectures

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Michael Opoku Agyeman,

Ali AhmadiniaAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 39, Issue 4

Pages 106 - 107

https://doi.org/10.1145/2082156.2082187

Published: 19 December 2011 Publication History

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Abstract

Three dimensional Network-on-Chip (3D NoC) architectures have evolved with a lot of interest to address the on-chip communication delays of modern SoC systems. However, the vertical interconnections between layers is more power and area hungry compared to 2D interconnections. In this paper we propose area efficient and low power heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D mesh topologies. Experimental results show a negligible penalty of up to 5% in average packet latency of 3D homogeneous NoC with bus hybrid routers. The heterogeneity however provides superiority of up to 67% and 19.7% in power and area efficiency of the NoC resources, respectively.

References

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D. Velenis, M. Stucchi, E. Marinissen, B. Swinnen, and E. Beyne. Impact of 3d design choices on manufacturing cost. In International Conference on 3D System Integration (3DIC), pages 1--5, 2009.

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T. T. Ye, G. D. Micheli, and L. Benini. Analysis of power consumption on switch fabrics in network routers. In Proceedings of Design Automation Conference (DAC), pages 524--529, 2002.

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Opoku Agyeman MGuerrero AVien Q(2022)Classification Techniques for Arrhythmia Patterns Using Convolutional Neural Networks and Internet of Things (IoT) DevicesIEEE Access10.1109/ACCESS.2022.319239010(87387-87403)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3192390
Challabi ORaghad ZAgyeman M(2019)A Study of FPGA-Based Supercomputing PlatformsProceedings of the 2019 3rd International Symposium on Computer Science and Intelligent Control10.1145/3386164.3386165(1-5)Online publication date: 25-Sep-2019
https://dl.acm.org/doi/10.1145/3386164.3386165

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cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 39, Issue 4

September 2011

116 pages

ISSN:0163-5964

DOI:10.1145/2082156

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Association for Computing Machinery

New York, NY, United States

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Published: 19 December 2011

Published in SIGARCH Volume 39, Issue 4

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Opoku Agyeman MGuerrero AVien Q(2022)Classification Techniques for Arrhythmia Patterns Using Convolutional Neural Networks and Internet of Things (IoT) DevicesIEEE Access10.1109/ACCESS.2022.319239010(87387-87403)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3192390
Challabi ORaghad ZAgyeman M(2019)A Study of FPGA-Based Supercomputing PlatformsProceedings of the 2019 3rd International Symposium on Computer Science and Intelligent Control10.1145/3386164.3386165(1-5)Online publication date: 25-Sep-2019
https://dl.acm.org/doi/10.1145/3386164.3386165

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Silicon-photonic network architectures for scalable, power-efficient multi-chip systems

Silicon-photonic network architectures for scalable, power-efficient multi-chip systems

3D floorplanning of low-power and area-efficient Network-on-Chip architecture

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