Anindita Chakraborty
Abstract
Non-binary number systems are increasingly gaining popularity in signal processing applications for their capabilities of handling arithmetic operations efficiently. One such number system, "Double Base Number System (DBNS)" has gained attention to many researchers for it's capability of performing multiplication operation efficiently. Recently, "Triple Base Number System (TBNS)" has been introduced which shows better performance over DBNS for higher bit operations in terms of speed, hardware complexity and power dissipation. However, the advantages of TBNS systems cannot be exploited due to substantial overhead of conversion from binary to TBNS. Keeping this issue in view, in this paper, a novel architecture has been proposed for high performance binary to TBNS conversion. Efficiency of this conversion scheme has been dealt with in details and experimental results and analysis clearly indicate the novelty of the architecture.
- Amitabha Sinha, Subhasis Maitra, Pavel Sinha, Ken Newton and Kishanu Mukherjee, "Triple Based Number Systems-A Novel Concept for Performance Enhancement of Digital Signal Processors", TENCON 2008 IEEE Region 10 Conference,19-21 Nov,2008, Hyderabad, pp. 1--5, Print ISBN 978-1-4244-2408-5.Google Scholar
- Subhasis Maitra, Amitabha Sinha, "A Single Digit Triple Base Number System-A new Concept for Implementing High Performance Multiplier Unit for DSP Applications", 6th International Conference on Information, Communications & Signal Processing, 2007, Singapore, pp. 1,Print ISBN 978-1-4244-0983-9.Google Scholar
- Uwe Meyer Baese "Digital Signal Processing with Field Programmable Gate Arrays", 2nd ed., Springer 2003.Google Scholar
- John P Hayes "Computer Architecture and Organization", Tata McGraw-Hill 2004. Google ScholarDigital Library
- V.S. Dimitrov, G.A. Jullien and W.C. Miller, 1999, "Theory and Applications of the Double-Base Number System", IEEE Trans. Computers, Vol. 48, 10, pp. 1098--1106. Google ScholarDigital Library
- Reto Zimmermann, "Lecture notes on Computer Arithmetic: Principles, Architectures and VLSI Design", Integrated Systems Laboratory, Swiss Federal Institute of Technology (ETH), Zurich, March 16, 1999.Google Scholar
- R. Muscedere, G.A. Jullien, V.S. Dimitrov and W.C. Miller, "Efficient Techniques for Binary-to-Multidigit Multidimensional Logarithmic Number System Conversion Using Range-Addressable Look-up Tables", IEEE Trans. Computers, Vol. 64, No. 3,pp. 257--269, March 2005. Google ScholarDigital Library
- V. Dimitrov, Saeid Sadeghi-Emamchaie, G.A. Jullien and W.C. Miller, "A Near Canonic Double-Based Number System (DBNS) with Applications in Digital Signal Processing", Proceedings SPIE Conference on Advanced Signal Processing, August 1996.Google ScholarCross Ref
- G.A. Jullien, V.S. Dimitrov, B. Li, W.C. Miller, A. Lee and M. Ahmadi, "A Hybrid DBNS Processor for DSP Computation", Proceedings International Symposium on Circuits and Systems, 1999.Google ScholarCross Ref
- V.S. Dimitrov, G.A. Jullien and W.C. Miller "An Algorithm for Modular Exponentiation", Information Processing Letters, vol. 66, no.3, pp. 155--159, 1998. Google ScholarDigital Library
- Xilinx, "Introduction and Overview", Virtex-II Pro Platform FPGAs March 9th, 2004.Google Scholar
- Roberto Muscedere, "A Hardware Efficient Very Large Bit Word Binary to Double Base Number System Converter for Encryption Applications", IEEE International Symposium on Circuits and Systems, New Orleans, LA, 27-30 May 2007, pp. 1373--1376.Google Scholar
- Guillaume Gilbert and J.M. Pierre Langlois, "Multipath Greedy Algorithm for Canonical Representation of Numbers in the Double Base Number System", IEEE-NEWCAS Conference, pp. 39--42, 2005.Google ScholarCross Ref
- Mikko Pankaala, Ari Passio, Mika Laiho, "Implementation Alternatives of a DBNS Adder", 9th International Workshop on Cellular Neural Networks and Their Applications, pp. 138--141, 2005.Google Scholar
- Manideepa Mukherjee, Amitabha Sinha, "A novel architecture for conversion of binary to single digit double base numbers", ACM SIGARCH Computer Architecture News ,Volume 38 ,Issue 5, pp. 1--6, December 2010, New York, NY, USA. Google ScholarDigital Library
Index Terms
- Conversion of binary to single-term triple base numbers for DSP applications
Recommendations
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays
Development of modern integrated circuit technologies makes it feasible to develop cheaper, faster and smaller special purpose signal processing function circuits. Digital Signal processing functions are generally implemented either on ASICs with ...
A study of decimal left shifters for binary numbers
The importance of decimal floating-point (DFP) arithmetic has been growing in the last years, and specifications for it are included in the revised IEEE 754 Standard for Floating-Point Arithmetic (IEEE 754-2008). IEEE 754-2008 specifies a binary ...
On Implementation of LUT with Large Numbers of Inputs (Abstract Only)
FPGA '15: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysA LUT is implemented with a set of flipflops which are connected to a series of multiplexers, or alternatively with a small memory, and needs exponentially many storage elements with respect to the numbers of inputs. Due to this FPGA uses LUTs having ...
Comments