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Multi-DaC programming model: a variant of multi-BSP model for divide-and-conquer algorithms

Published: 28 January 2012 Publication History

Abstract

Nowadays, the evolution of multi-core architectures goes towards increasing the number of cores and levels of cache. Meanwhile, current typical parallel programming models are unable to exploit the potential of these processors efficiently. In order to achieve desired performance on these hardwares we need to understand architectural parameters appropriately and also apply them in algorithm design. Computational models such as Multi-BSP, illustrate these parameters and explain adequate methods for designing algorithms on multi-cores. One of the most applicable categories of problems is Divide-and-Conquer (DaC) that needs to be adapted by such model for implementing on these systems.
In this paper, we have attempted to make a mapping between DaC tree and the Memory Hierarchy (MH) of multi-core processor. Multi-BSP model inspired us to introduce Multi-DaC programming model. Analogous to Multi-BSP analysis, lower bounds for communication and synchronization costs have been presented in the paper respecting DaC algorithms. This work is a step towards making multi-core programming easy and tries to obtain correct analysis of DaC algorithm behavior on multi-core architectures.

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  • (2012)A Bridging Model for Branch-and-Bound Algorithms on Multi-core ArchitecturesProceedings of the 2012 Fifth International Symposium on Parallel Architectures, Algorithms and Programming10.1109/PAAP.2012.41(235-241)Online publication date: 17-Dec-2012

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cover image ACM Conferences
DAMP '12: Proceedings of the 7th workshop on Declarative aspects and applications of multicore programming
January 2012
62 pages
ISBN:9781450311175
DOI:10.1145/2103736
  • General Chair:
  • Umut Acar,
  • Program Chair:
  • Vítor Santos Costa
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 28 January 2012

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Author Tags

  1. cache
  2. divide-and-conquer
  3. memory hierarchy
  4. multi-BSP
  5. multi-core architectures
  6. parallel

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View all
  • (2022)High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and FrameworksIEEE Access10.1109/ACCESS.2022.320110710(90429-90455)Online publication date: 2022
  • (2012)A Bridging Model for Branch-and-Bound Algorithms on Multi-core ArchitecturesProceedings of the 2012 Fifth International Symposium on Parallel Architectures, Algorithms and Programming10.1109/PAAP.2012.41(235-241)Online publication date: 17-Dec-2012

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