skip to main content
10.1145/2107763.2107775acmotherconferencesArticle/Chapter ViewAbstractPublication PagesinaConference Proceedingsconference-collections
research-article

Quest for the ultimate network-on-chip: the NaNoC project

Published:25 January 2012Publication History

ABSTRACT

The NaNoC project is progressing toward an innovative design platform for multicore systems based on future networks-on-chip. This platform enables the design, manufacturing and management of networks-on-chip by tackling new requirements of future systems like virtualization, power, thermal and application management, as well as new challenges in technology scaling like reliability and variability. The introduction of networks-on-chip into the platform enables a component-oriented architectural design which is out of reach of current design methods. This paper presents an overview of the achievements at the end of the second out of three years of planned activities.

References

  1. S. Rodrigo, S. Medardoni, J. Flich, D. Bertozzi, and J. Duato. Efficient implementation of distributed routing algorithms for NoCs. IET Computers and Digital Techniques, 3:460--475, 2009.Google ScholarGoogle ScholarCross RefCross Ref
  2. F. O. Sem-Jacobsen, S. Rodrigo Mocholi, A. Strano, T. Skeie, D. Bertozzi, and F. Gilabert. Enabling power efficiency through dynamic rerouting on-chip. ACM TECS Special Issue on On-Chip and Off-Chip Network Architectures, 2011.Google ScholarGoogle Scholar
  3. T. Skeie, F. O. Sem-Jacobsen, S. Rodrigo Mocholi, J. Flich, D. Bertozzi, and S. Medardoni. Flexible dor routing for virtualization of multicore chips. In International Symposium on System-on-Chip, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. A. Strano, C. G. Requena, D. Ludovici, M. E. Gomez, and M. Favalli. Exploiting network-on-chip structural redundancy for a cooperative and scalable built-in self-test architecture. In Proceedings of DATE, 2011.Google ScholarGoogle ScholarCross RefCross Ref
  5. X. Wang, M. Yang, Y. Jiang, and P. Liu. On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks. Microprocessors and Microsystems, 35(2):119--129, Mar. 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. F.-C. Yang, Y.-T. Lin, S. Kundu, C.-F. Kao, and I.-J. Huang. An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL. 19 NO. 4, March 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. H. Yi, S. Park, and S. Kundu. A Design-for-Debug (DfD) for NoC-based SoC Debugging via NoC. 17th Asian Test Symposium, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. J. Zhang, M. Yan, and S. Li. Debug Support for Scalable System-on-Chip. Seventh International Workshop on Microprocessor Test and Verification, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Quest for the ultimate network-on-chip: the NaNoC project

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in
    • Published in

      cover image ACM Other conferences
      INA-OCMC '12: Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
      January 2012
      51 pages
      ISBN:9781450310109
      DOI:10.1145/2107763

      Copyright © 2012 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 25 January 2012

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article

      Acceptance Rates

      Overall Acceptance Rate12of27submissions,44%

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader