ABSTRACT
Softcore processors are an attractive alternative to using radiation-hardened processors in space-based applications. Unlike traditional processors however, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). This paper applies two common SEU mitigation techniques, TMR with checkpointing and DWC with checkpointing, to the LEON3 softcore processor. The improvement in reliabilty over an unmitigated version of the processor is measured using three metrics: the architectural vulnerability factor (AVF), mean time to failure (MTTF), and mean useful instructions to failure (MuITF). Using configuration memory fault injection, we found that DWC with checkpointing improves the MTTF and MuITF by over 35x, and that TMR with triplicated input and outputs improves the MTTF and MITF by over 6000x.
- Q. Zhou, K. Mohanram, Gate sizing to radiation harden combinational logic, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 25 (1) (2006) 155 -- 166. Google ScholarDigital Library
- J. F. Bell, et al., Mars reconnaissance orbiter mars color imager (MARCI): Instrument description, calibration, and performance, Journal of Geophysical Research 114.Google Scholar
- L. Sterpone, M. S. Reorda, M. Violante, F. L. Kastensmidt, L. Carro, Evaluating different solutions to design fault tolerant systems with SRAM-based FPGAs, Journal of Electronic Testing: Theory and Applications 23 (2007) 47--54. Google ScholarDigital Library
- A. Ziv, J. Bruck, Analysis of checkpointing schemes with task duplication, Computers, IEEE Transactions on 47 (2) (1998) 222--227. Google ScholarDigital Library
- S. S. Mukherjee, et al., A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, Microarchitecture, IEEE/ACM International Symposium on 0 (2003) 29. Google ScholarDigital Library
- C. Weaver, et al., Techniques to reduce the soft error rate of a high-performance microprocessor, SIGARCH Comput. Archit. News 32 (2004) 264--. Google ScholarDigital Library
- J. Gaisler, E. Catovic, Multi-Core Processor Based on LEON3-FT IP Core (LEON3-FT-MP), in: DASIA 2006 - Data Systems in Aerospace, Vol. 630 of ESA Special Publication, 2006.Google Scholar
- D. Pradhan, N. Vaidya, Roll-forward and rollback recovery: performance-reliability trade-off, in: Fault-Tolerant Computing, 1994. FTCS-24. Digest of Papers., Twenty-Fourth International Symposium on, 1994, pp. 186--195.Google Scholar
- H. Zhou, A case for fault tolerance and performance enhancement using chip multi-processors, Computer Architecture Letters 5 (1) (2006) 22--25. Google ScholarDigital Library
- R. Hillman, et al., Space processor radiation mitigation and validation techniques for an 1,800 MIPS processor board, in: Radiation and Its Effects on Components and Systems, 2003. RADECS 2003. Proceedings of the 7th European Conference on, 2003, pp. 347 -- 352.Google Scholar
- S. S. Mukherjee, M. Kontz, S. K. Reinhardt, Detailed design and evaluation of redundant multithreading alternatives, Computer Architecture, International Symposium on 0 (2002) 0099. Google ScholarDigital Library
- E. Johnson, M. Caffrey, P. Graham, N. Rollins, M. Wirthlin, Accelerator validation of an FPGA SEU simulator, Nuclear Science, IEEE Transactions on 50 (6) (2003) 2147--2157.Google Scholar
Index Terms
- Reliability of a softcore processor in a commercial SRAM-based FPGA
Recommendations
Dynamically reconfigurable register file for a softcore VLIW processor
DATE '10: Proceedings of the Conference on Design, Automation and Test in EuropeThis paper presents dynamic reconfiguration of a register file of a Very Long Instruction Word (VLIW) processor implemented on an FPGA. We developed an open-source reconfigurable and parameterizable VLIW processor core based on the VLIW Example (VEX) ...
Comments