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Reliability of a softcore processor in a commercial SRAM-based FPGA

Published: 22 February 2012 Publication History

Abstract

Softcore processors are an attractive alternative to using radiation-hardened processors in space-based applications. Unlike traditional processors however, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). This paper applies two common SEU mitigation techniques, TMR with checkpointing and DWC with checkpointing, to the LEON3 softcore processor. The improvement in reliabilty over an unmitigated version of the processor is measured using three metrics: the architectural vulnerability factor (AVF), mean time to failure (MTTF), and mean useful instructions to failure (MuITF). Using configuration memory fault injection, we found that DWC with checkpointing improves the MTTF and MuITF by over 35x, and that TMR with triplicated input and outputs improves the MTTF and MITF by over 6000x.

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Cited By

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  • (2021)Methods for Improving the Reliability of Intelligent Semiconductor2021 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia)10.1109/ICCE-Asia53811.2021.9641987(1-4)Online publication date: 1-Nov-2021
  • (2017)Reliability Improvement of Hardware Task Graphs via Configuration Early FetchIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263172425:4(1408-1420)Online publication date: 1-Apr-2017
  • (2012)Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial ReconfigurationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E95.A.2347E95.A:12(2347-2356)Online publication date: 2012
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  1. Reliability of a softcore processor in a commercial SRAM-based FPGA

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      cover image ACM Conferences
      FPGA '12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
      February 2012
      352 pages
      ISBN:9781450311557
      DOI:10.1145/2145694
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 22 February 2012

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      Author Tags

      1. AVF
      2. MTTF
      3. MuITF
      4. softcore processors

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      FPGA '12 Paper Acceptance Rate 20 of 87 submissions, 23%;
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      View all
      • (2021)Methods for Improving the Reliability of Intelligent Semiconductor2021 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia)10.1109/ICCE-Asia53811.2021.9641987(1-4)Online publication date: 1-Nov-2021
      • (2017)Reliability Improvement of Hardware Task Graphs via Configuration Early FetchIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263172425:4(1408-1420)Online publication date: 1-Apr-2017
      • (2012)Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial ReconfigurationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E95.A.2347E95.A:12(2347-2356)Online publication date: 2012
      • (2012)Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration2012 International Conference on Field-Programmable Technology10.1109/FPT.2012.6412137(220-223)Online publication date: Dec-2012

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