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OCTAVO: an FPGA-centric processor family

Published: 22 February 2012 Publication History

Abstract

Overlay processor architectures allow FPGAs to be programmed by non-experts using software, but prior designs have mainly been based on the architecture of their ASIC predecessors. In this paper we develop a new processor architecture that from the beginning accounts for and exploits the predefined widths, depths, maximum operating frequencies, and other discretizations and limits of the underlying FPGA components. The result is Octavo, a ten-pipeline-stage eight-threaded processor that operates at the block RAM maximum of 550MHz on a Stratix IV FPGA. Octavo is highly parameterized, allowing us to explore trade-offs in datapath and memory width, memory depth, and number of supported thread contexts.

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cover image ACM Conferences
FPGA '12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
February 2012
352 pages
ISBN:9781450311557
DOI:10.1145/2145694
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 22 February 2012

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Author Tags

  1. FPGA
  2. microarchitecture
  3. multithreading
  4. soft processor

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FPGA '12 Paper Acceptance Rate 20 of 87 submissions, 23%;
Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

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  • (2022)PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software developmentProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507740(933-945)Online publication date: 28-Feb-2022
  • (2022)Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator CompilationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.311685933:6(1478-1490)Online publication date: 1-Jun-2022
  • (2021)A Highly-Efficient and Tightly-Connected Many-Core Overlay ArchitectureIEEE Access10.1109/ACCESS.2021.30741719(65277-65292)Online publication date: 2021
  • (2019)FPGA-Based Processor Acceleration for Image Processing ApplicationsJournal of Imaging10.3390/jimaging50100165:1(16)Online publication date: 13-Jan-2019
  • (2019)Time-Multiplexed FPGA Overlay ArchitecturesACM Transactions on Design Automation of Electronic Systems10.1145/333986124:5(1-19)Online publication date: 23-Jul-2019
  • (2017)Microarchitectural Comparison of the MXP and Octavo Soft-Processor FPGA OverlaysACM Transactions on Reconfigurable Technology and Systems10.1145/305367910:3(1-25)Online publication date: 27-May-2017
  • (2016)Exploiting Configuration Dependencies for Rapid Area-efficient Customization of Soft-core ProcessorsProceedings of the 19th International Workshop on Software and Compilers for Embedded Systems10.1145/2906363.2906385(163-172)Online publication date: 23-May-2016
  • (2015)On Data Forwarding in Deeply Pipelined Soft ProcessorsProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689067(181-189)Online publication date: 22-Feb-2015
  • (2015)Area-Efficient Near-Associative Memories on FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/26294717:4(1-22)Online publication date: 23-Jan-2015
  • (2015)Custom FPGA-based soft-processors for sparse graph acceleration2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP.2015.7245698(9-16)Online publication date: Jul-2015
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