skip to main content
10.1145/2145694.2145734acmconferencesArticle/Chapter ViewAbstractPublication PagesfpgaConference Proceedingsconference-collections
research-article

A lean FPGA soft processor built using a DSP block

Published:22 February 2012Publication History

ABSTRACT

As Field Programmable Gate Arrays (FPGAs) have advanced, the capabilities and variety of embedded resources have increased. In the last decade, signal processing has become one of the main driving applications for FPGA adoption, so FPGA vendors tailored their architectures to such applications. The resulting embedded digital signal processing (DSP) blocks have now advanced to the point of supporting a wide range of operations. In this paper, we explore how these DSP blocks can be applied to general computation. We show that the DSP48E1 blocks in Xilinx Virtex-6 devices support a wide range of standard processor instructions which can be designed into the core of a basic processor with minimal additional logic usage.

References

  1. S. Chalamalasetti, S. Purohit, M. Margala, and W. Vanderbauwhede. MORA - an architecture and programming model for a resource efficient coarse grained reconfigurable processor. In NASA/ESA Conf. on Adaptive Hardware and Systems (AHS), pages 389--396, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. X. Chu and J. McAllister. FPGA based soft-core SIMD processing: A MIMO-OFDM fixed-complexity sphere decoder case study. In Proc. Int. Conf. on Field Programmable Technology (FPT), pages 479--484, 2010.Google ScholarGoogle ScholarCross RefCross Ref
  3. X. Chu, J. McAllister, and R. Woods. A pipeline interleaved heterogeneous SIMD soft processor array architecture for MIMO-OFDM detection. In Proc. Int. Symp. on Applied Reconfigurable Computing (ARC), pages 133--144, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. M. Milford and J. McAllister. An ultra-fine processor for FPGA DSP chip multiprocessors. In Asilomar Conf. on Signals, Systems and Computers, pages 226 --230, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Xilinx Inc. Virtex-6 FPGA DSP48E1 User Guide, 2011.Google ScholarGoogle Scholar
  6. P. Yiannacouras, J. Steffan, and J. Rose. Application-specific customization of soft processor microarchitecture. In Proc. ACM/SIGDA Int. Symp. on Field Programmable Gate Arrays (FPGA), pages 201--210, Feb. 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. P. Yiannacouras, J. Steffan, and J. Rose. VESPA: Portable, scalable, and flexible FPGA-based vector processors. In Proc. Int. Conf. on Compilers, Architecture and Synthesis for Embedded Systems (CASES), pages 61--70, Oct. 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. J. Yu, G. Lemieux, and C. Eagleston. Vector processing as a soft-core CPU accelerator. In Proc. ACM/SIGDA Int. Symp. on Field Programmable Gate Arrays (FPGA), pages 222--232, Feb. 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. A lean FPGA soft processor built using a DSP block

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in
      • Published in

        cover image ACM Conferences
        FPGA '12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
        February 2012
        352 pages
        ISBN:9781450311557
        DOI:10.1145/2145694

        Copyright © 2012 ACM

        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 22 February 2012

        Permissions

        Request permissions about this article.

        Request Permissions

        Check for updates

        Qualifiers

        • research-article

        Acceptance Rates

        FPGA '12 Paper Acceptance Rate20of87submissions,23%Overall Acceptance Rate125of627submissions,20%

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader