Fatemeh Sadat Pourhashemi
ABSTRACT
Designing with field-programmable gate arrays (FPGAs) can face with difficulties due to process variations. Some techniques use reconfigurability of FPGAs to reduce the effects of process variations in these chips. Furthermore, FPGA architecture enhancement is an effective way to degrade the impact of variation. In this paper, various FPGA architectures are examined to identify which architecture can achieve larger parametric yield improvement utilizing multiple configurations as opposed to single configuration. Experimental results show that by increasing cluster size from 4 to 10, yield improvement increases from 2.82X to 4.48X. However, changing look-up table (LUT) size from 4 to 7 results in yield improvement degradation from 2.82X to 1.45X, using 10 configurations compared to single configuration over 20 MCNC benchmark circuits. These results indicate that multi-configuration technique causes larger timing yield improvement in FPGAs with larger cluster size and smaller LUT size.
- Y. Lin, M. Hutton, and L. He, "Placement and timing for FPGAs considering variations," in Proceedings of the International Conference on Field Programmable Logic and Applications, pp. 1--7, 2006.Google Scholar
- Y. Matsumoto, M. Hioki, T. Kawanami, H. Koike, T. Tsutsumi, T. Nakagawa and T. Sekigawa, "Suppression of intrinsic delay variation in FPGAs using multiple configurations," ACM Transactions on Reconfigurable Technology and Systems, vol. 1, no. 1, pp. 1--31, 2008. Google ScholarDigital Library
- L. Cheng, J. Xiong, L. He and M. Hutton, "FPGA performance optimization via chipwise placement considering process variations," in Proceedings of the International Conference on Field Programmable Logic and Applications, pp. 1--6, 2006.Google Scholar
- H. Wong, L. Cheng, Y. Lin and L. He, "FPGA device and architecture evaluation considering process variations," in Proceedings of International Conference on Computer-Aided Design, pp. 19--24, 2005. Google ScholarDigital Library
- A. Kumar and M. Anis, "FPGA design for timing yield under process variations," IEEE Transactions on Very Large Scale Integration Systems, vol. 18, no. 3, pp. 423--435, 2010. Google ScholarDigital Library
- K. A. Bowman, S. G. Duvall, and J. M. Meindl, "Impact of Die-to-Die and Within-Die Parameter Fluctuations on The Maximum Clock Frequency Distribution for Gigascale Integration," IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 183--190, 2002.Google ScholarCross Ref
- G. Nabaa, N. Azizi, and F. N. Najm, "An adaptive FPGA architecture with process variation compensation and reduced leakage," in Proceedings of the 43rd Design Automation Conference, pp. 624--629, 2006. Google ScholarDigital Library
- Y. Sugihara, Y. Kume, K. Kobayashi, and H. Onodera, "Performance optimization by track swapping on critical paths utilizing random variations for FPGAs," Proceedings of International Conference on Field Programmable Logic and Applications, pp. 503--506, 2008.Google Scholar
- E. Ahmed, "The effect of logic block granularity on deep-submicron FPGA performance and density." MS thesis, Dept. of Electrical and Computer Engineering, University of Toronto, Canada, 2001.Google Scholar
- J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, W. Fang and J. Rose, "VPR 5.0: FPGA CAD architecture exploration tools with single-driver routing, heterogeneity and process scaling," IEEE International Symposium on Field Programmable Gate Arrays, pp. 133--142, 2009. Google ScholarDigital Library
- VPR and T-VPack: Versatile Packing, Placement and Routing for FPGAs." http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html. Last checked June 19, 2009.Google Scholar
- S. R. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A. Tiwari and J. Torrellas, "VARIUS: a model of process variation and resulting timing errors for micro-architectures," IEEE Transactions on Semiconductor Manufacturing, vol. 21, no. 1, pp. 3--13, 2008.Google ScholarCross Ref
- A. Bsoul, "Reliability and variation-aware placement for field programmable gate arrays," MS thesis, Dept. of Electrical and Computer Engineering, Queen's University, Canada, 2009.Google Scholar
Index Terms
- Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only)
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