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Scalable architecture for 135 GBPS IPv6 lookup on FPGA (abstract only)

Published: 22 February 2012 Publication History

Abstract

High-speed IP lookup remains a challenging problem in next generation routers due to the ever increasing line rate and routing table size. In addition, the evolution towards IPv6 also requires long prefix length, sparse prefix distribution, and potentially very large routing tables. In this paper, we propose a novel Combined Length-Infix Pipelined Search (CLIPS) architecture for IPv6 routing table lookup on FPGA. CLIPS solves the longest prefix match (LPM) problem by combining both prefix length and infix pattern search. Binary search in prefix length is performed on the 64-bit routing prefix of IPv6 down to an 8-bit length range in log(64/8)=3 phases; each phase performs a fully-pipelined infix pattern search with only one external memory access. A fourth and the last phase then finds the LPM (if any) within the 8-bit length range in a compressed multi-bit trie.
We describe the algorithms and data structures used for the CLIPS construction, run-time operation, dynamic update and false-positive avoidance. The proposed solution improves the on-chip memory efficiency on FPGA and maximizes the external SRAM utilization; additional properties for ensuring the practicality of our scheme include the modular construction, easy dynamic update, and simple resource allocation. Using a state-of-the-art FPGA, our CLIPS prototype supports up to 2.7 millioin IPv6 prefixes when employing 33 Mbits of BRAM and 4 channels of external SRAM. The prototype achieves a sustained throughput of 264 million IPv6 lookups per second, or 135 Gbps with minimum size (64-byte) packets.

References

[1]
R. Zemach, CRS-1 Overview, http://www.slideshare.net/wjunjmt/cisco-crs1, Mar 2007.
[2]
C. Hermsmeyer, H. Song, R. Schlenk, R. Gemelli, and S. Bunse, Towards 100G Packet Processing: Challenges and Technologies, in Bell Labs Technical Journal, vol. 14, no. 2, Aug 2009, pp. 57--79.
[3]
Growth of the BGP Table - 1994 to Present, http://bgp.potaroo.net/, 12 2010.
[4]
The BGP Instability Report, http://bgpupdates.potaroo.net/instability/bgpupd.html, Dec. 2010.
[5]
M. Bando and J. Chao, Flashtrie: Hash-based prefix-compressed trie for ip route lookup beyond 100gbps, in INFOCOM, 2010.
[6]
H. Fadishei, M. S. Zamani, and M. Sabaei, A novel reconfigurable hardware architecture for IP address lookup, in Proc. ANCS, 2005, pp. 81--90.
[7]
M. Behdadfar, H. Saidi, H. Alaei, and B. Samari, Scalar Prefix Search: A New Route Lookup Algorithm for Next Generation Internet, in IEEE INFOCOM, 2009.
[8]
D. Lin, Y. Zhang, C. Hu, B. Liu, X. Zhang, and D. Pao, Route table partitioning and load balancing for parallel searching with TCAMs, in Proc. IPDPS, 2007, pp. 1--10.
[9]
M. J. Akhbarizadeh, M. Nourani, R. Panigrahy, and S. Sharma, A TCAM-based parallel architecture for high-speed packet forwarding, IEEE Trans. Comput., vol. 56, no. 1, pp. 58--72, 2007.
[10]
F. Zane, G. J. Narlikar, and A. Basu, CoolCAMs: Power-efficient TCAMs for forwarding engines. in Proc. INFOCOM, 2003, pp. 42--52.
[11]
K. Zheng, C. Hu, H. Lu, and B. Liu, A TCAM-based distributed parallel IP lookup scheme and performance analysis, IEEE/ACM Trans. Netw., vol. 14, no. 4, pp. 863--875, 2006.
[12]
W. Eatherton, G. Varghese, and Z. Dittia, Tree bitmap: Hardware/Software IP Lookups with Incremental Updates, SIGCOMM Comput. Commun. Rev., vol. 34, no. 2, pp. 97--122, 2004.
[13]
W. Jiang and V. K. Prasanna, A memory-balanced linear pipeline architecture for trie-based IP lookup, in Proc. Hot Interconnects (HotI '07), 2007, pp. 83--90.
[14]
W. Lu and S. Sahni, Packet forwarding using pipelined multibit tries, in Proc. ISCC, 2006, pp. 802--807.
[15]
H. Song, J. Turner, and J. Lockwood, Shape shifting trie for faster IP router lookup, in Proc. ICNP, 2005, pp. 358--367.
[16]
H. Le and V. Prasanna, Scalable High Throughput and Power Efficient IP-Lookup on FPGA, in Proc. of 17th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2009.
[17]
H. Lu and S. Sahni, A B-Tree Dynamic Router-Table Design, IEEE Trans. Comput., vol. 54, no. 7, pp. 813--824, 2005.
[18]
M. Waldvogel, G. Varghese, J. Turner, and B. Plattner, Scalable high speed IP routing lookups, in Proc. SIGCOMM, 1997, pp. 25--38.
[19]
K. S. Kim and S. Sahni, IP Lookup by Binary Search on Prefix Length, in Proc. Eighth IEEE Intl. Symp. on Computers and Communication (ISCC), 2003.
[20]
M. Waldvogel, G. Varghese, J. Turner, and B. Plattner, Scalable High-Speed Prefix Matching, ACM Trans. Comput. Syst., vol. 19, pp. 440--482, 2001.
[21]
Y.-H. E. Yang, O. Erdem, and V. K. Prasanna, High performance ip lookup on fpga with combined length-infifix pipelined search, in Poster Session of Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on, may 2011, pp. 77--80.
[22]
Y.-H. E. Yang and V. K. Prasanna, High Throughput and Large Capacity Pipelined Dynamic Search Tree on FPGA, in Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2010.
[23]
RIS Raw Data, http://data.ris.ripe.net.
[24]
M. Wang, S. Deering, T. Hain, and L. Dunn, Non-random generator for ipv6 tables, in High Performance Interconnects, 2004. Proceedings. 12th Annual IEEE Symposium on, aug. 2004, pp. 35--40.
[25]
M. Bando and H. J. Chao, Flashtrie: hash-based prefix-compressed trie for ip route lookup beyond 100gbps, in Proceedings of the 29th conference on Information communications, ser. INFOCOM'10, 2010, pp. 821--829.
[26]
F. Baboescu, D. M. Tullsen, G. Rosu, and S. Singh, A tree based router search engine architecture with single port memories, in Proc. ISCA, 2005, pp. 123--133.

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    cover image ACM Conferences
    FPGA '12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
    February 2012
    352 pages
    ISBN:9781450311557
    DOI:10.1145/2145694

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    Published: 22 February 2012

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    Author Tags

    1. binary search tree
    2. ip lookup
    3. longest prefix match
    4. packet forwarding
    5. search trie
    6. tree bitmap

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