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Novel pulsed-latch replacement based on time borrowing and spiral clustering

Published: 25 March 2012 Publication History

Abstract

Flip-flops are the most common form of sequencing elements; however, they have a significantly higher sequencing overhead than latches in terms of delay, power, and area. Hence, pulsed-latches are promising to reduce power for high performance circuits. In this paper, we propose a novel pulsed-latch replacement approach to save power and satisfy timing constraints. We fully utilize the intrinsic time borrowing property of pulsed-latches and develop a spiral clustering method with clock gating consideration. In addition, spiral clustering works well for both rectangular and rectilinear shaped layouts; the latter are popular in modern IC design. Experimental results show that our approach can generate very power efficient results.

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Cited By

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  • (2021)Power-Efficient Bidirectional Shift Register Using Conditional Bidirectional Pulsed Latch CircuitAdvances in Energy Technology10.1007/978-981-16-1476-7_12(123-130)Online publication date: 28-Jul-2021
  • (2018)Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8351251(1-5)Online publication date: May-2018
  • (2017)Near- and Sub- $V_{t}$ Pipelines Based on Wide-Pulsed-Latch Design TechniquesIEEE Journal of Solid-State Circuits10.1109/JSSC.2017.271792752:9(2475-2487)Online publication date: Sep-2017
  • Show More Cited By

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      cover image ACM Conferences
      ISPD '12: Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
      March 2012
      220 pages
      ISBN:9781450311670
      DOI:10.1145/2160916
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 25 March 2012

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      Author Tags

      1. clock power
      2. pulsed-latch
      3. pulsed-register
      4. time borrowing

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      March 25 - 28, 2012
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      Overall Acceptance Rate 62 of 172 submissions, 36%

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      Cited By

      View all
      • (2021)Power-Efficient Bidirectional Shift Register Using Conditional Bidirectional Pulsed Latch CircuitAdvances in Energy Technology10.1007/978-981-16-1476-7_12(123-130)Online publication date: 28-Jul-2021
      • (2018)Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8351251(1-5)Online publication date: May-2018
      • (2017)Near- and Sub- $V_{t}$ Pipelines Based on Wide-Pulsed-Latch Design TechniquesIEEE Journal of Solid-State Circuits10.1109/JSSC.2017.271792752:9(2475-2487)Online publication date: Sep-2017
      • (2014)Power optimization for clock network with clock gate cloning and flip-flop mergingProceedings of the 2014 on International symposium on physical design10.1145/2560519.2560520(77-84)Online publication date: 30-Mar-2014
      • (2013)Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock GatingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.223482832:2(242-246)Online publication date: 1-Feb-2013
      • (2012)PlacementProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429442(283-290)Online publication date: 5-Nov-2012

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