research-article

A universal parallel front-end for execution driven microarchitecture simulation

Authors:

Chad D. Kersey,

Arun Rodrigues,

Sudhakar YalamanchiliAuthors Info & Claims

RAPIDO '12: Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

Pages 25 - 32

https://doi.org/10.1145/2162131.2162135

Published: 23 January 2012 Publication History

Abstract

Execution driven microarchitecture simulators tend to devote a large portion of their source code to a front-end that performs instruction set level functional simulation, providing the decoded instruction stream to a back-end that performs timing simulation. In this paper we introduce the current incarnation of QSim, a universal front-end for execution driven multicore microarchitecture simulators. QSim adapts the popular and portable QEMU full-system emulator to a thread safe, instruction set neutral API, running unmodified application binaries in a lightly modified Linux operating system. QSim has been shown to support at least 512 emulated hardware threads, each running in a separate host thread.

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Cited By

Sharan HVutukuru MPanda B(2023)DDIOSim: A Microarchitecture Simulator for Data Direct I/O Technology2023 IEEE 30th International Conference on High Performance Computing, Data, and Analytics (HiPC)10.1109/HiPC58850.2023.00035(184-188)Online publication date: 18-Dec-2023
https://doi.org/10.1109/HiPC58850.2023.00035
Cota ECarloni LSartor JNaik MRossbach C(2019)Cross-ISA machine instrumentation using fast and scalable dynamic binary translationProceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments10.1145/3313808.3313811(74-87)Online publication date: 14-Apr-2019
https://dl.acm.org/doi/10.1145/3313808.3313811
Parikh NGohil VAwasthi MShorey RMurty RChen YJamieson K(2018)METAProceedings of the 24th Annual International Conference on Mobile Computing and Networking10.1145/3241539.3267737(774-776)Online publication date: 15-Oct-2018
https://dl.acm.org/doi/10.1145/3241539.3267737
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Index Terms

A universal parallel front-end for execution driven microarchitecture simulation
1. Hardware
  1. Hardware validation

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Published In

cover image ACM Other conferences

RAPIDO '12: Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

January 2012

44 pages

ISBN:9781450311144

DOI:10.1145/2162131

Conference Chairs:
Daniel Gracia Pérez
CEA LIST, France
,
Smail Niar
University of Valenciennes/INRIA, France
,
Cristina Silvano
Politecnico di Milano, Italy
,
Morteza Biglari Abhari
The University of Auckland, New Zealand

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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HiPEAC: HiPEAC Network of Excellence

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 January 2012

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Division of Computer and Network Systems

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RAPIDO '12

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HiPEAC

RAPIDO '12: Methods and Tools

January 23, 2012

Paris, France

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Overall Acceptance Rate 14 of 28 submissions, 50%

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Cited By

Sharan HVutukuru MPanda B(2023)DDIOSim: A Microarchitecture Simulator for Data Direct I/O Technology2023 IEEE 30th International Conference on High Performance Computing, Data, and Analytics (HiPC)10.1109/HiPC58850.2023.00035(184-188)Online publication date: 18-Dec-2023
https://doi.org/10.1109/HiPC58850.2023.00035
Cota ECarloni LSartor JNaik MRossbach C(2019)Cross-ISA machine instrumentation using fast and scalable dynamic binary translationProceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments10.1145/3313808.3313811(74-87)Online publication date: 14-Apr-2019
https://dl.acm.org/doi/10.1145/3313808.3313811
Parikh NGohil VAwasthi MShorey RMurty RChen YJamieson K(2018)METAProceedings of the 24th Annual International Conference on Mobile Computing and Networking10.1145/3241539.3267737(774-776)Online publication date: 15-Oct-2018
https://dl.acm.org/doi/10.1145/3241539.3267737
Kang SKang JHa SMudge TPnevmatikatos D(2018)Fast parallel simulation of a manycore architecture with a flit-level on-chip network modelProceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1145/3229631.3229647(115-122)Online publication date: 15-Jul-2018
https://dl.acm.org/doi/10.1145/3229631.3229647
Ahmed KLiu JBadawy AEidenbenz S(2017)A brief history of HPC simulation and future challengesProceedings of the 2017 Winter Simulation Conference10.5555/3242181.3242210(1-12)Online publication date: 3-Dec-2017
https://dl.acm.org/doi/10.5555/3242181.3242210
Ahmed KLiu JBadawy AEidenbenz S(2017)A brief history of HPC simulation and future challenges2017 Winter Simulation Conference (WSC)10.1109/WSC.2017.8247804(419-430)Online publication date: Dec-2017
https://doi.org/10.1109/WSC.2017.8247804
Cota EMantovani PCarloni L(2016)Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator IntegrationProceedings of the 2016 International Conference on Supercomputing10.1145/2925426.2926258(1-12)Online publication date: 1-Jun-2016
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Wang JDong ZYalamanchili SRiley G(2016)FNMACM Transactions on Modeling and Computer Simulation10.1145/273563026:2(1-26)Online publication date: 29-Jan-2016
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Cota EMantovani PDi Guglielmo GCarloni L(2015)An Analysis of Accelerator Coupling in Heterogeneous ArchitecturesProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744794(1-6)Online publication date: 7-Jun-2015
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Song WMukhopadhyay SYalamanchili S(2015)KitFox: Multiphysics Libraries for Integrated Power, Thermal, and Reliability Simulations of Multicore MicroarchitectureIEEE Transactions on Components, Packaging and Manufacturing Technology10.1109/TCPMT.2015.24851585:11(1590-1601)Online publication date: Nov-2015
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