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SNR analysis approach for hardware/software partitioning using dynamically adaptable fixed point representation

Published: 03 May 2012 Publication History

Abstract

During the early design phases of software development, many developers use floating point data types and libraries but often convert these applications into fixed point representations in later design phases - a time consuming process often requiring significant designer effort. While various approaches have been proposed to automate the floating to fixed point conversion process, these approaches are mainly targeted at creating optimized software implementations and do not directly support partitioning floating point implementation to hardware. We present an approach to optimize the number of bits required for a dynamically adaptable fixed-point representation using SNR analysis methods targeting computationally intensive floating-point kernels. We present a hardware/software partitioning methodology that leverages this SNR analysis to partition application kernels to custom hardware coprocessors implemented within a field-programmable gate array. Using several case study applications, we highlight the performance benefits and area requirements of the resulting hardware implementations.

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      cover image ACM Conferences
      GLSVLSI '12: Proceedings of the great lakes symposium on VLSI
      May 2012
      388 pages
      ISBN:9781450312448
      DOI:10.1145/2206781
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      Published: 03 May 2012

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      Author Tags

      1. floating point profiling
      2. floating point to fixed point conversion
      3. hardware/software partitioning
      4. signal to noise ratio

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      May 3 - 4, 2012
      Utah, Salt Lake City, USA

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