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Memory-based computing for performance and energy improvement in multicore architectures

Authors:

Kamran Rahmani,

Prabhat Mishra,

Swarup BhuniaAuthors Info & Claims

GLSVLSI '12: Proceedings of the great lakes symposium on VLSI

Pages 287 - 290

https://doi.org/10.1145/2206781.2206851

Published: 03 May 2012 Publication History

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Abstract

Memory-based computing (MBC) is promising for improving performance and energy efficiency in both data- and compute-intensive applications. In this paper, we propose a novel reconfigurable MBC framework for multicore architectures where each core uses caches for computation using Look Up Tables (LUTs). Experimental results demonstrate that on-demand memory-based computing in each core can significantly improve performance (up to 4.7X, 3.3X on average) as well as reduce energy consumption (up to 4.7X, 2X on average) in multicore architectures.

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Cited By

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Ahmed AHuang YMishra P(2019)Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy OptimizationACM Transactions on Embedded Computing Systems10.1145/330976218:2(1-24)Online publication date: 2-Apr-2019
https://dl.acm.org/doi/10.1145/3309762
Diguet JOnizawa NRizk MSepulveda JBaghdadi AHanyu T(2018)Networked Power-Gated MRAMs for Memory-Based ComputingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.285645826:12(2696-2708)Online publication date: Dec-2018
https://doi.org/10.1109/TVLSI.2018.2856458
Rizk MDiguet JOnizawa NBaghdadi ASepulveda MAkgul YGripon VHanyu T(2017)NoC-MRAM architecture for memory-based computing: Database-search case study2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS.2017.8010167(309-312)Online publication date: Jun-2017
https://doi.org/10.1109/NEWCAS.2017.8010167
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Index Terms

Memory-based computing for performance and energy improvement in multicore architectures
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
      2. Self-organizing autonomic computing

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Published In

GLSVLSI '12: Proceedings of the great lakes symposium on VLSI

May 2012

388 pages

ISBN:9781450312448

DOI:10.1145/2206781

General Chairs:
Erik Brunvard
University of Utah, USA
,
Ken Stevens
University of Utah, USA
,
Program Chairs:
Joseph R. Cavallaro
Rice University, USA
,
Tong Zhang
Rensselaer Polytechnic Institute, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 03 May 2012

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GLSVLSI '12: Great Lakes Symposium on VLSI 2012

May 3 - 4, 2012

Utah, Salt Lake City, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Ahmed AHuang YMishra P(2019)Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy OptimizationACM Transactions on Embedded Computing Systems10.1145/330976218:2(1-24)Online publication date: 2-Apr-2019
https://dl.acm.org/doi/10.1145/3309762
Diguet JOnizawa NRizk MSepulveda JBaghdadi AHanyu T(2018)Networked Power-Gated MRAMs for Memory-Based ComputingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.285645826:12(2696-2708)Online publication date: Dec-2018
https://doi.org/10.1109/TVLSI.2018.2856458
Rizk MDiguet JOnizawa NBaghdadi ASepulveda MAkgul YGripon VHanyu T(2017)NoC-MRAM architecture for memory-based computing: Database-search case study2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS.2017.8010167(309-312)Online publication date: Jun-2017
https://doi.org/10.1109/NEWCAS.2017.8010167
Baharvand FMiremadi S(2015)ARMORProceedings of the 2015 IEEE 21st Pacific Rim International Symposium on Dependable Computing (PRDC)10.1109/PRDC.2015.25(215-224)Online publication date: 18-Nov-2015
https://dl.acm.org/doi/10.1109/PRDC.2015.25

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Recommendations

Energy-aware thread co-location in heterogeneous multicore processors

Analysis of computing and energy performance of multicore, NUMA, and manycore platforms for an irregular application

Massively LDPC Decoding on Multicore Architectures

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