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Looking back and looking forward: power, performance, and upheaval

Published: 01 July 2012 Publication History

Abstract

The past 10 years have delivered two significant revolutions. (1) Microprocessor design has been transformed by the limits of chip power, wire latency, and Dennard scaling---leading to multicore processors and heterogeneity. (2) Managed languages and an entirely new software landscape emerged---revolutionizing how software is deployed, is sold, and interacts with hardware. Researchers most often examine these changes in isolation. Architects mostly grapple with microarchitecture design through the narrow software context of native sequential SPEC CPU benchmarks, while language researchers mostly consider microarchitecture in terms of performance alone. This work explores the clash of these two revolutions over the past decade by measuring power, performance, energy, and scaling, and considers what the results may mean for the future. Our diverse findings include the following: (a) native sequential workloads do not approximate managed workloads or even native parallel workloads; (b) diverse application power profiles suggest that future applications and system software will need to participate in power optimization and management; and (c) software and hardware researchers need access to real measurements to optimize for power and energy.

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      cover image Communications of the ACM
      Communications of the ACM  Volume 55, Issue 7
      July 2012
      120 pages
      ISSN:0001-0782
      EISSN:1557-7317
      DOI:10.1145/2209249
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 01 July 2012
      Published in CACM Volume 55, Issue 7

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      • (2019)SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8714998(510-515)Online publication date: Mar-2019
      • (2017)Modeling the Power Variability of Core Speed Scaling on Homogeneous Multicore SystemsScientific Programming10.1155/2017/86869712017Online publication date: 1-Jan-2017
      • (2017)DyScale: A MapReduce Job Scheduler for Heterogeneous Multicore ProcessorsIEEE Transactions on Cloud Computing10.1109/TCC.2015.24157725:2(317-330)Online publication date: 1-Apr-2017
      • (2017)Energy consumption of synchronization algorithms in distributed simulationsJournal of Simulation10.1057/s41273-016-0036-711:3(242-252)Online publication date: 19-Dec-2017
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      • (2016)Maximizing Performance Under a Power CapACM SIGOPS Operating Systems Review10.1145/2954680.287237550:2(545-559)Online publication date: 25-Mar-2016
      • (2016)Maximizing Performance Under a Power CapACM SIGPLAN Notices10.1145/2954679.287237551:4(545-559)Online publication date: 25-Mar-2016
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