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Directed test generation for validation of multicore architectures

Published: 05 July 2012 Publication History

Abstract

Functional validation is widely acknowledged as a major challenge for multicore architectures. Directed tests are promising since a significantly smaller number of directed tests can achieve the same coverage goal compared to constrained-random tests. SAT-based bounded model checking is effective for automated generation of directed tests (counterexamples). While existing approaches focus on clause forwarding between different bounds to reduce the test generation time, this article proposes a novel technique that exploits temporal, structural, and spatial symmetry in multicore designs at the same time. Our proposed technique enables the reuse of the knowledge learned from one core to the remaining cores in multicore architectures (structural symmetry), from one bound to the next for a give property (temporal symmetry), as well as from one property to other properties (spatial symmetry). The experimental results demonstrate that our approach can significantly (3--10 times) reduce overall test generation time compared to existing approaches.

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    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 17, Issue 3
    Special section on verification challenges in the concurrent world
    June 2012
    377 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/2209291
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 05 July 2012
    Accepted: 01 December 2011
    Revised: 01 October 2011
    Received: 01 May 2011
    Published in TODAES Volume 17, Issue 3

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    Author Tags

    1. Multicore architecture
    2. SAT solving
    3. bounded model checking
    4. test generation

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    • (2022)A Survey on Assertion-based Hardware VerificationACM Computing Surveys10.1145/351057854:11s(1-33)Online publication date: 9-Sep-2022
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