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High-performance clock mesh optimization

Published: 05 July 2012 Publication History

Abstract

Clock meshes are extremely effective at producing low-skew regional clock networks that are tolerant of environmental and process variations. For this reason, clock meshes are used in most high-performance designs, but this robustness consumes significant power. In this work, we present two techniques to optimize high-performance clock meshes. The first technique is a mesh perturbation methodology for nonuniform mesh routing. The second technique is a skew-aware buffer placement through iterative buffer deletion. We demonstrate how these optimizations can achieve significant power reductions and a near elimination of short-circuit power. In addition, the total wire length is decreased, the number of required buffers is decreased, and both skew and robustness are improved on average when variation is considered.

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    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 17, Issue 3
    Special section on verification challenges in the concurrent world
    June 2012
    377 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/2209291
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 05 July 2012
    Accepted: 01 December 2011
    Revised: 01 October 2011
    Received: 01 May 2011
    Published in TODAES Volume 17, Issue 3

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    Author Tags

    1. Clock mesh optimization
    2. robust design

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    • (2024)Redefining Clock Network Construction: The Nested Flex Paradigm for Enhanced PPA Dynamics2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558222(1-5)Online publication date: 19-May-2024
    • (2024)Clock mesh synthesis through dynamic programming with physical parameters considerationIntegration10.1016/j.vlsi.2024.102261(102261)Online publication date: Aug-2024
    • (2023)Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling2023 IEEE 36th International System-on-Chip Conference (SOCC)10.1109/SOCC58585.2023.10256966(1-6)Online publication date: 5-Sep-2023
    • (2023)Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323866(1-9)Online publication date: 28-Oct-2023
    • (2022)Buffer Reduction for Congestion Control during Timing Optimization2022 IEEE 2nd International Conference on Power, Electronics and Computer Applications (ICPECA)10.1109/ICPECA53709.2022.9719205(36-40)Online publication date: 21-Jan-2022
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