Kuan-Yu Lin
Abstract
Power consumption is known to be a crucial issue in current IC designs. To tackle this problem, Multiple Dynamic Supply Voltage (MDSV) designs are proposed as an efficient solution for power savings. However, the increasing variability of clock skew during the switching of power modes leads to an increase in the complication of clock skew reduction in MDSV designs. In this article, we propose a load-balanced clock tree synthesizer with Adjustable Delay Buffer (ADB) insertion for clock skew reduction in MDSV designs. The clock tree synthesizer adopts the Minimum Spanning Tree (MST) metric to estimate the interconnect capacitance and execute the graph-theoretic clustering. The power-mode-guided optimization is also embedded into the clock tree synthesizer for improving additional area overhead in the step of ADB insertion. After constructing the initial buffered clock tree, we insert the ADBs with delay value assignments to reduce clock skew in MDSV designs. The ADBs can be used to produce additional delays, hence the clock latencies and skew become tunable in a clock tree. An efficient algorithm of ADB insertion for the minimization of clock skew, area, and runtime in MDSV designs has been presented. Comparing with the state-of-the-art algorithm of ADB insertion, experimental results show maximum 42.40% area overhead improvement. With the power-mode-guided optimization, the maximum improvement of area overhead can increase to 47.87%.
- Chao, T.-H., Hsu, Y.-C., Ho, J.-M., and B., K. A. 1992. Zero skew clock routing with minimum wirelength. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 39, 11, 799--814.Google Scholar
- Chen, Y. P. and Wong, D. F. 1996. An algorithm for zero-skew clock tree routing with buffer insertion (edtc'96). In Proceedings of the European Design and Test Conference. IEEE Computer Society, Los Alamitos, CA, 230--236. Google ScholarDigital Library
- Edahiro, M. 1993. A clustering-based optimization algorithm in zero-skew routings. In Proceedings of the ACM/IEEE Design Automation Conference (DAC'93). ACM, New York, 612--616. Google ScholarDigital Library
- Edahiro, M. 1994. An efficient zero-skew routing algorithm. In Proceedings of the ACM/IEEE Design Automation Conference (DAC'94). ACM, New York, 375--380. Google ScholarDigital Library
- Hu, S. and Hu, J. 2007. Unified adaptivity optimization of clock and logic signals. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD'07). IEEE Computer Society, Los Alamitos, CA, 125--130. Google ScholarDigital Library
- Jain, A. K., Murty, M. N., and Flynn, P. J. 1999. Data clustering: a review. ACM Comput. Surv. 31, 3, 264--323. Google ScholarDigital Library
- Johnston, T. K. 1999. Clock tree adjustable buffer. U. S. Patent 7571406B2.Google Scholar
- Khandelwal, V. and Srivastava, A. 2007. Variability-Driven formulation for simultaneous gate sizing and post-silicon tunability allocation. In Proceedings of the International Symposium on Physical Design (ISPD'07). ACM, New York, 11--18. Google ScholarDigital Library
- Kurd, N. A., Barkarullah, J. S., Dizon, R. O., Fletcher, T. D., and Madland, P. D. 2001. A multigigahertz clocking scheme for the pentium 4 microprocessor. IEEE J. Solid-State Circ. 36, 11, 1647--1653.Google ScholarCross Ref
- Liu, I.-M., Chou, T.-L.,Wong, D. F., and Aziz, A. 2000. Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. In Proceedings of the International Symposium on Physical Design (ISPD'00). ACM, New York, 33--38. Google ScholarDigital Library
- Lung, C.-L., Zeng, Z.-Y., Chou, C.-H., and Chang, S.-C. 2010. Clock skew optimization considering complicated power modes. In Proceedings of the Conference on Design, Automation, and Test in Europe (DATE'10). 1474--1480. Google ScholarDigital Library
- Mehta, A. D., Chen, Y.-P., Menezes, N., Wong, D. F., and Pileggi, L. T. 1997. Clustering and load balancing for buffered clock tree synthesis. In Proceedings IEEE International Conference on Computer Design (ICCD'97). IEEE Computer Society, Los Alamitos, CA, USA, 217--223. Google ScholarDigital Library
- R.-S., Tsay. 1993. An exact zero-skew clock routing algorithm. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 12, 2, 242--249. Google ScholarDigital Library
- Roberts, G. N. 1994. Adjustable buffer driver. U. S. Patent 5361003.Google Scholar
- Shelar, R. S. 2007. An efficient clustering algorithm for low power clock tree synthesis. In Proceedings of the International Symposium on Physical Design (ISPD'07). ACM, New York, 181--188. Google ScholarDigital Library
- Su, Y.-S., Hon, W.-K., Yang, C.-C., Chang, S.-C., and Chang, Y.-J. 2010. Clock skew minimization in multi-voltage mode designs using adjustable delay buffers. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 29, 12, 1921--1930. Google ScholarDigital Library
- Takahashi, E., Kasai, Y., Murakawa, M., and Higuchi, T. 2003. A post-silicon clock timing adjustment using genetic algorithms. In Digest of Technical Papers of the Symposium on VLSI Circuits. 13--16.Google Scholar
- Tam, S., Limaye, R. D., and Desai, U. N. 2003. Clock generation and distribution for the 130-nm itaniumr 2 processor with 6-mb on-die l3 cache. IEEE J. Solid-State Circ. 39, 4, 636--642.Google ScholarCross Ref
- Tam, S., Rusu, S., Desai, U. N., Kim, R., Zhang, J., and Young, I. 2000. Clock generation and distribution for the first ia-64 microprocessor. IEEE J. Solid-State Circ. 35, 11, 1545--1552.Google ScholarCross Ref
- Tsai, J.-L., Chen, T.-H., and C. C.-P., C. 2004. Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 23, 4, 565--572. Google ScholarDigital Library
- Tsai, J.-L., Zhang, L., and Che, C. C.-P. 2005. Statistical timing analysis driven post-silicon-tunable clock-tree synthesis. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD'05). IEEE Computer Society, Los Alamitos, CA, 575--581. Google ScholarDigital Library
Index Terms
- Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs
Recommendations
Low Voltage Clock Tree Synthesis with Local Gate Clusters
GLSVLSI '19: Proceedings of the 2019 on Great Lakes Symposium on VLSIIn this paper, a novel local clock gate cluster-aware low voltage clock tree synthesis methodology is introduced. In low voltage/swing clocking, timing closure is a challenging problem due to tight skew and slew constraints. The clock gating makes this ...
Low-Power Clock Tree Synthesis for 3D-ICs
We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees’ dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock ...
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSIIt is well known that clock skew minimization becomes critical in high-performance VLSI designs. In this paper, the assignment of adjustable delay buffers(ADBs) is applied to minimize the clock skew in a buffered clock tree in a multi-voltage mode ...
Comments