Tomoyuki Nagatsuka
ABSTRACT
We propose CoreSymphony architecture, which aims at balancing single-thread performance and multi-thread performance on CMPs. The former version of CoreSymphony had complex branch predictor, re-order buffer, and in-order state management mechanism. In this paper, we solve these problems and evaluate the performance of CoreSymphony.
- M. D. Hill, et al. Amdahl's Law in the Multicore Era. IEEE Computer, 41(7):33--38, 2008. Google Scholar
Digital Library
- N. Fujieda, et al. A MIPS System Simulator SimMips for Education and Research of Computer Science. In IPSJ Journal, Vol.50, No.11, pages 2665--2676, 2009.Google Scholar
- R. Rakvic, et al. Completion Time Multiple Branch Prediction for Enhancing Trace Cache Performance. In Proceedings of the 27th International Symposium on Computer Architecture (ISCA-2000), pages 47--58, 2000. Google ScholarDigital Library
- T. Nagatsuka, et al. CoreSymphony: An Efficient Reconfigurable Multi-core Architecture. In ACM SIGARCH Computer Architecture News, Vol.39, Iss.4, pages 32--37, 2011. Google ScholarDigital Library
Index Terms
- CoreSymphony architecture
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