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A semiempirical model for wakeup time estimation in power-gated logic clusters

Published: 03 June 2012 Publication History

Abstract

Wakeup time is an important overhead that must be determined for effective power gating, particularly in logic clusters that undergo frequent mode transitions for run-time leakage power reduction. In this paper, a semiempirical model for virtual supply voltage in terms of basic parameters of the power-gated circuit is presented. Hence a closed-form expression for estimation of wakeup time of a power-gated logic cluster is derived. Experimental results of application of the model to ISCAS85 benchmark circuits show that wakeup time may be estimated within an average error of 16.3% across 22x variation in sleep transistor sizes and 13x variation in circuit sizes with significant speedup in computation time compared to SPICE level circuit simulations.

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Cited By

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  • (2019)Power-Gating Models for Rapid Design Exploration2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS44328.2019.8961232(1-4)Online publication date: Jun-2019
  • (2016)Macromodels for Static Virtual Ground Voltage Estimation in Power-Gated CircuitsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2015.250427063:5(468-472)Online publication date: May-2016
  • (2014)Compiler-Assisted Leakage- and Temperature- Aware Instruction-Level VLIW SchedulingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.227179422:6(1416-1428)Online publication date: Jun-2014
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    cover image ACM Conferences
    DAC '12: Proceedings of the 49th Annual Design Automation Conference
    June 2012
    1357 pages
    ISBN:9781450311991
    DOI:10.1145/2228360
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 03 June 2012

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    Author Tags

    1. design automation
    2. leakage current
    3. power gating
    4. wakeup time

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    June 3 - 7, 2012
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    View all
    • (2019)Power-Gating Models for Rapid Design Exploration2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS44328.2019.8961232(1-4)Online publication date: Jun-2019
    • (2016)Macromodels for Static Virtual Ground Voltage Estimation in Power-Gated CircuitsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2015.250427063:5(468-472)Online publication date: May-2016
    • (2014)Compiler-Assisted Leakage- and Temperature- Aware Instruction-Level VLIW SchedulingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.227179422:6(1416-1428)Online publication date: Jun-2014
    • (2013)Compiler-assisted leakage energy optimization of media applications on stream architecturesInternational Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2013.6523599(120-127)Online publication date: Mar-2013

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