research-article

Cost-effective power delivery to support per-core voltage domains for power-constrained processors

Authors:

Hamid Reza Ghasemi,

Abhishek A. Sinkar,

Michael J. Schulte,

Nam Sung KimAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 56 - 61

https://doi.org/10.1145/2228360.2228372

Published: 03 June 2012 Publication History

Abstract

Per-core voltage domains can improve performance under a power constraint. Most commercial processors, however, only have one chip-wide voltage domain because splitting the voltage domain into per-core voltage domains and powering them with multiple off-chip voltage regulators (VRs) incurs a high cost for the platform and package designs. Although using on-chip switching VRs can be an alternative solution, integrating high-quality inductors and cores on the same chip has been a technical challenge. In this paper, we propose a cost-effective power delivery technique to support per-core voltage domains. Our technique is based on the observations that (i) core-to-core voltage variations are relatively small for most execution intervals when the voltages/frequencies are optimized to maximize performance under a power constraint and (ii) per-core power-gating devices augmented with small circuits can serve as low-cost VRs that can provide high efficiency in situations like (i). Our experimental results show that processors using our technique can achieve power efficiency as high as those using per-core on-chip switching VRs at much lower cost.

References

[1]

W. Kim, M. S. Gupta, G.-Y. Wei, and D. Brooks, "System Level Analysis of Fast, Per-core DVFS using On-chip Switching Regulators," in IEEE/ACM Int. Symp. on High-Perf. Comp. Arch. (HPCA), 2008, pp. 123--134.

[2]

R. Teodorescu and J. Torrellas, "Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors," in IEEE/ACM Int. Symp. on Comp. Arch. (ISCA), 2008, pp. 363--374.

Digital Library

[3]

A. R. Alameldeen et al., "Evaluating Non-Deterministic Multi-Threaded Commercial Workloads," in Comp. Arch. Evaluation using Commercial Workloads (CAECW), 2002, pp. 30--38.

[4]

Princeton University. PARSEC Benchmark Suite. {Online}. http://parsec.cs.princeton.edu/

[5]

M. M. K. Martin et al., "Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset," SIGARCH Comput. Archit. News, vol. 33, no. 4, pp. 92--99, Nov 2005.

Digital Library

[6]

D. M. Brooks et al., "Power-aware Microarchitecture: Design and Modeling Challenges for next-generation microprocessors," IEEE Micro, vol. 8, no. 6, pp. 26--44, Nov/Dec 2000.

Digital Library

[7]

S. Rusu et al., "A 45 nm 8-Core Enterprise Xeon® Processor," IEEE J. of Solid-State Circuits (JSSC), vol. 45, no. 1, pp. 7--14, Jan 2010.

[8]

N. S. Kim et al., "Frequency and Yield optimization using Power Gates in Power-Constrained Designs," in IEEE/ACM Int. Symp. on Low Power Electronics and Design (ISLPED), 2009, pp. 121--126.

Digital Library

[9]

P. Hazucha et al., "High Voltage Tolerant Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters," IEEE J. of Solid-State Circuits, vol. 42, no. 1, pp. 66--73, Jan 2007.

[10]

Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, "A 5-GHz Mesh Interconnect for a Teraflops Processor," IEEE Micro, vol. 27, no. 5, pp. 51--61, Sep/Oct 2007.

Digital Library

[11]

W. Fu and A. Fayed, "A feasibility study of high-frequency buck regulators in nanometer CMOS technologies," in IEEE Dallas Circuits and Systems Workshop (DCAS), 2009, pp. 1--4.

[12]

P Hazucha et al., "Area-Efficient Linear Regulator With Ultra-Fast Load Regulation," IEEE J. of Solid State Circuits (JSSC), vol. 40, no. 4, pp. 933--940, Apr 2005.

[13]

Jon Klein. (2006) Fairchild Semiconductors. {Online}. http://www.fairchildsemi.com/an/AN/AN-6005.pdf

[14]

P. Hazucha et al., "A 233-MHz 80%-87% Efficient Four-Phase DC-DC Converter utilizing Air-core Inductors on Package," IEEE J. of Solid-State Circuits (JSSC), vol. 40, no. 4, pp. 838--845, Apr 2005.

[15]

J. Lee, G. Hatcher, L. Vandenberghe, and C. K. Yang, "Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies," IEEE T. on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 9, pp. 1017--1027, Sep 2007.

Digital Library

[16]

K. Aygun, M. J. Hill, K. Eilert, K. Radhakrishnan, and A. Levin, "Power Delivery for High-performance Microprocessor," Intel Technology J., vol. 9, no. 4, pp. 273--283, Nov 2005.

[17]

McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures. {Online}. http://www.hpl.hp.com/research/mcpat

[18]

S. Sarangi et al., "VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects," IEEE T. on Semiconductor Manufacturing, vol. 21, no. 1, pp. 3--13, Feb 2008.

Cited By

Zou AZhu HLeng JHe XReddi VGill CZhang X(2021)System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery SystemACM Transactions on Architecture and Code Optimization10.1145/346814518:4(1-27)Online publication date: 3-Sep-2021
https://dl.acm.org/doi/10.1145/3468145
Torng CPan POu YTan CBatten C(2021)Ultra-Elastic CGRAs for Irregular Loop Specialization2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00042(412-425)Online publication date: Feb-2021
https://doi.org/10.1109/HPCA51647.2021.00042
Hajiamini SShirazi BCrandall AGhasemzadeh HCain C(2018)Impact of Cache Voltage Scaling on Energy-Time Pareto Frontier in Multicore SystemsSustainable Computing: Informatics and Systems10.1016/j.suscom.2018.02.01118(54-65)Online publication date: Jun-2018
https://doi.org/10.1016/j.suscom.2018.02.011
Show More Cited By

Index Terms

Cost-effective power delivery to support per-core voltage domains for power-constrained processors
1. Hardware
  1. Very large scale integration design
    1. VLSI system specification and constraints

Recommendations

Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors

Per-core voltage domains can improve performance under a power constraint. Most commercial processors, however, only have a single voltage domain for all processor cores. This is because splitting the single voltage domain into per-core voltage domains ...
Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors
DATE '14: Proceedings of the conference on Design, Automation & Test in Europe

Design of power delivery system has great influence on the power management in many-core processor systems. Moving voltage regulators from off-chip to on-chip gains more and more interest in the power delivery system design, because it is able to ...
Distributed LDO regulators in a 28 nm power delivery system

A fully integrated power delivery system with distributed on-chip low-dropout (LDO) regulators developed for voltage regulation in portable devices and fabricated in a 28 nm CMOS process is described. Each LDO employs adaptive bias for fast and power ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 June 2012

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Division of Computing and Communication Foundations

Conference

DAC '12

Sponsor:

EDAC
SIGDA

DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

18
Total Citations
View Citations
437
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 05 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Zou AZhu HLeng JHe XReddi VGill CZhang X(2021)System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery SystemACM Transactions on Architecture and Code Optimization10.1145/346814518:4(1-27)Online publication date: 3-Sep-2021
https://dl.acm.org/doi/10.1145/3468145
Torng CPan POu YTan CBatten C(2021)Ultra-Elastic CGRAs for Irregular Loop Specialization2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00042(412-425)Online publication date: Feb-2021
https://doi.org/10.1109/HPCA51647.2021.00042
Hajiamini SShirazi BCrandall AGhasemzadeh HCain C(2018)Impact of Cache Voltage Scaling on Energy-Time Pareto Frontier in Multicore SystemsSustainable Computing: Informatics and Systems10.1016/j.suscom.2018.02.01118(54-65)Online publication date: Jun-2018
https://doi.org/10.1016/j.suscom.2018.02.011
Zou ALeng JZu YTong TReddi VBrooks DWei GZhang X(2017)IvoryProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062268(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062268
Li HWang XXu JWang ZMaeda RWang ZYang PDuong LWang Z(2017)Energy-Efficient Power Delivery System Paradigms for Many-Core ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258405636:3(449-462)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2584056
Pothukuchi RAnsari AGopireddy BTorrellas J(2017)Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT.2017.23(260-272)Online publication date: Sep-2017
https://doi.org/10.1109/PACT.2017.23
Torng CWang MBatten C(2016)Asymmetry-aware work-stealing runtimesACM SIGARCH Computer Architecture News10.1145/3007787.300114244:3(40-52)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1145/3007787.3001142
Torng CWang MBatten CMin SLoh G(2016)Asymmetry-aware work-stealing runtimesProceedings of the 43rd International Symposium on Computer Architecture10.1109/ISCA.2016.14(40-52)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1109/ISCA.2016.14
Torrellas J(2016)Extreme-scale computer architectureNational Science Review10.1093/nsr/nwv0853:1(19-23)Online publication date: 6-Jan-2016
https://doi.org/10.1093/nsr/nwv085
He XYan GHan YLi X(2016)Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage ComputingJournal of Computer Science and Technology10.1007/s11390-016-1625-731:2(253-266)Online publication date: 7-Mar-2016
https://doi.org/10.1007/s11390-016-1625-7
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten