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Algorithms and data structures for fast and good VLSI routing

Authors:

Jens VygenAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 459 - 464

https://doi.org/10.1145/2228360.2228441

Published: 03 June 2012 Publication History

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Abstract

We present advanced data structures and algorithms for fast and high-quality global and detailed routing in modern technologies. Global routing is based on a combinatorial approximation scheme for min-max resource sharing. Detailed routing uses exact shortest path algorithms, based on a shape-based data structure for pin access and a two-level track-based data structure for long-distance connections. All algorithms are very fast. We demonstrate their superiority over traditional approaches by a comparison to an industrial router (on 32nm and 22nm chips). Our router is over two times faster, has 5% less netlength, 20% less vias, and reduces detours by more than 90%.

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Cited By

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E VS SR AM IB AK S(2024)Advancing VLSI Routing Algorithms through Machine Learning Techniques2024 International Conference on Emerging Research in Computational Science (ICERCS)10.1109/ICERCS63125.2024.10895082(1-8)Online publication date: 12-Dec-2024
https://doi.org/10.1109/ICERCS63125.2024.10895082
Yao PZhang PZhu W(2023)Pathfinding Model and Lagrangian-Based Global Routing2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247969(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247969
Jia XCai YZhou QYu B(2018)A Multicommodity Flow-Based Detailed Router With Efficient Acceleration TechniquesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269327037:1(217-230)Online publication date: Jan-2018
https://doi.org/10.1109/TCAD.2017.2693270
Show More Cited By

Index Terms

Algorithms and data structures for fast and good VLSI routing
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Very large scale integration design

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Published In

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

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Published: 03 June 2012

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DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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E VS SR AM IB AK S(2024)Advancing VLSI Routing Algorithms through Machine Learning Techniques2024 International Conference on Emerging Research in Computational Science (ICERCS)10.1109/ICERCS63125.2024.10895082(1-8)Online publication date: 12-Dec-2024
https://doi.org/10.1109/ICERCS63125.2024.10895082
Yao PZhang PZhu W(2023)Pathfinding Model and Lagrangian-Based Global Routing2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247969(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247969
Jia XCai YZhou QYu B(2018)A Multicommodity Flow-Based Detailed Router With Efficient Acceleration TechniquesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269327037:1(217-230)Online publication date: Jan-2018
https://doi.org/10.1109/TCAD.2017.2693270
Brazil MZachariasen MBrazil MZachariasen M(2015)Rectilinear Steiner TreesOptimal Interconnection Trees in the Plane10.1007/978-3-319-13915-9_3(151-218)Online publication date: 2015
https://doi.org/10.1007/978-3-319-13915-9_3
Jia XCai YZhou QChen GLi ZLi ZChang Y(2014)MCFRouteProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691446(397-404)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691446
Wei YSze CViswanathan NLi ZAlpert CReddy LHuber ATellez GKeller DSapatnekar S(2014)Techniques for scalable and effective routability evaluationACM Transactions on Design Automation of Electronic Systems10.1145/256666319:2(1-37)Online publication date: 28-Mar-2014
https://dl.acm.org/doi/10.1145/2566663
Jia XCai YZhou QChen GLi ZLi Z(2014)MCFRoute: A detailed router based on multi-commodity flow method2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2014.7001382(397-404)Online publication date: Nov-2014
https://doi.org/10.1109/ICCAD.2014.7001382
Zhang YChu C(2013)RegularRouteIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.221449121:9(1655-1668)Online publication date: 1-Sep-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2214491
Chang FTsay RMak WChen S(2013)MANAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.226587832:10(1557-1568)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1109/TCAD.2013.2265878
MaíBerg JNieberg T(2013)Rectilinear paths with minimum segment lengthsDiscrete Applied Mathematics10.1016/j.dam.2011.12.003161:12(1769-1775)Online publication date: 1-Aug-2013
https://dl.acm.org/doi/10.1016/j.dam.2011.12.003

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Abstract

References

Cited By

Index Terms

Recommendations

Area-I/O flip-chip routing for chip-package co-design considering signal skews

A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs

Full-Chip Routing Considering Double-Via Insertion

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