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Removing overhead from high-level interfaces

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Mark HorowitzAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 783 - 789

https://doi.org/10.1145/2228360.2228502

Published: 03 June 2012 Publication History

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Abstract

Hardware modules would be much easier to reuse if they supported generic flexible high-level interfaces. However, these interfaces are rarely used since they lead to timing and area overheads compared to a customized design. This paper describes a reachability analysis framework that identifies over-provisioning in instances of flexible design, and offers a technique for annotating this information so that modern synthesis tools can remove most of the overhead. Results are demonstrated on a variety of flexible structures, including functional blocks, programmable state machines, and latency-insensitive interfaces.

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Underwood AStine J(2023)Design Exploration of Magnitude Comparators for RISC-V System-on-Chip Architectures2023 57th Asilomar Conference on Signals, Systems, and Computers10.1109/IEEECONF59524.2023.10476937(1534-1538)Online publication date: 29-Oct-2023
https://doi.org/10.1109/IEEECONF59524.2023.10476937

Index Terms

Removing overhead from high-level interfaces
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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Published In

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGBED: ACM Special Interest Group on Embedded Systems

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New York, NY, United States

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Published: 03 June 2012

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DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

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Underwood AStine J(2023)Design Exploration of Magnitude Comparators for RISC-V System-on-Chip Architectures2023 57th Asilomar Conference on Signals, Systems, and Computers10.1109/IEEECONF59524.2023.10476937(1534-1538)Online publication date: 29-Oct-2023
https://doi.org/10.1109/IEEECONF59524.2023.10476937

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Recommendations

PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations

Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs

High-level design and validation of the BlueSPARC multithreaded processor

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