Wujie Wen
Yuan Xie
ABSTRACT
Process variations and thermal fluctuations significantly affect the write reliability of spin-transfer torque random access memory (STT-RAM). Traditionally, modeling the impacts of these variations on STT-RAM designs requires expensive Monte-Carlo runs with hybrid magnetic-CMOS simulation steps. In this paper, we propose a fast and scalable semi-analytical simulation method--PS3-RAM, for STT-RAM write reliability analysis. Simulation results show that PS3-RAM offers excellent agreement with the conventional simulation method without running the costly macro-magnetic and SPICE simulations. Our method can accurately estimate the STT-RAM write error rate at both MTJ switching directions under different temperatures while receiving a speedup of multiple orders of magnitude (five order or more). PS3-RAM shows great potentials in the STT-RAM reliability analysis at the early design stage of memory or micro-architecture.
- BSIM. http://www-device.eecs.berkeley.edu/bsim3/. UC Berkeley.Google Scholar
- X. Cong, N. Dimin, Z. Xiaochun, K. H. Seung, N. Matt, and Y. Xie. "Device Architecture Co-Optimization of STT-RAM Based Memory for Low Power Embedded Systems". In ICCAD, pages 463--470, Nov 2011. Google ScholarDigital Library
- P. Doubilet, C. Begg, M. Weinstein, P. Braun, and B. McNeil. "Probabilistic Sensitivity Analysis Using Monte Carlo Simulation. A Practical Approach". 1985.Google Scholar
- F. Harris. "On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform". Proceedings of the IEEE, 66(1):51--83, Jan. 1978.Google ScholarCross Ref
- J. Li, H. Liu, S. Salahuddin, and K. Roy. "Variation-Tolerant Spin-Torque Transfer (STT) MRAM Array for Yield Enhancement". In CICC, pages 193--196, Sep. 2008.Google ScholarCross Ref
- P. T. M. (PTM). http://www.eas.asu.edu/ptm/. ASU.Google Scholar
- B. Sheu, D. Scharfetter, P.-K. Ko, and M.-C. Jeng. "BSIM: Berkeley short-channel IGFET model for MOS transistors". JSSC, 22(4):558--566, Aug 1987.Google Scholar
- R. Singha, A. Balijepalli, A. Subramaniam, F. Liu, and S. Nassif. "Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation". In 44th DAC, pages 823--828, June 2007. Google ScholarDigital Library
- C. W. Smullen, A. Nigam, S. Gurumurthi, and M. R. Stan. "The STeTSiMS STT-RAM Simulation and Modeling System". In ICCAD, pages 318--325, Nov 2011. Google ScholarDigital Library
- G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen. "A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs". In 15th HPCA, pages 239--249. IEEE, 2009.Google ScholarCross Ref
- X. Wang, Y. Zheng, H. Xi, and D. Dimitrov. "Thermal Fluctuation Effects on Spin Torque Induced Switching: Mean and Variations". JAP, 103(3):034507-034507-4, Feb. 2008.Google ScholarCross Ref
- W. Xu, Y. Chen, X. Wang, and T. Zhang. "Improving STT MRAM storage density through smaller-than-worst-case transistor sizing". In 46th DAC, pages 87--90, July 2009. Google ScholarDigital Library
- W. Xu, H. Sun, Y. Chen, and T. Zhang. "Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT-RAM)". In IEEE Trans. on VLSI System, pages 483--493. IEEE, 2011. Google ScholarDigital Library
- Y. Ye, F. Liu, S. Nassif, and Y. Cao. "Statistical Modeling and Simulation of Threshold Variation under Dopant Fluctuations and Line-Edge Roughness". In 45th DAC, pages 900--905, June 2008. Google ScholarDigital Library
- Y. Zhang, X. Wang, and Y. Chen. "STT-RAM Cell Design Optimization for Persistent and Non-Persistent Error rate Reduction: A statistcal Design View". In ICCAD, pages 471--477, Nov. 2011. Google ScholarDigital Library
- P. Zhou, B. Zhao, J. Yang, and Y. Zhang. "Energy Reduction for STT-RAM Using Early Write Termination". In ICCAD, pages 264--268. ACM, 2009. Google ScholarDigital Library
Index Terms
- PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method
Recommendations
State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System
DAC '14: Proceedings of the 51st Annual Design Automation ConferenceMulti-level Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising nonvolatile memory technology for high-capacity and high-performance applications. However, the reliability concerns and the complicated access mechanism greatly ...
MTJ variation monitor-assisted adaptive MRAM write
DAC '16: Proceedings of the 53rd Annual Design Automation ConferenceSpin-transfer torque random access memory (STT-RAM) and magnetoelectric random access memory (MeRAM) are promising non-volatile memory technologies. But STT-RAM and Me RAM both suffer from high write error rate due to thermal fluctuation of ...
Processor caches with multi-level spin-transfer torque ram cells
ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and designIt has been predicted that a processor's caches could occupy as much as 90% of chip area for technology nodes from the current. In this paper, we study the use of multi-level spin-transfer torque RAM (STT-RAM) cells in the design of processor caches. ...
Comments