research-article

Rank idle time prediction driven last-level cache writeback

Authors:

Samira M. Khan,

Daniel A. JiménezAuthors Info & Claims

MSPC '12: Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness

Pages 21 - 29

https://doi.org/10.1145/2247684.2247690

Published: 16 June 2012 Publication History

Abstract

In modern DDRx memory systems, memory write requests can cause significant performance loss by increasing the memory access latency for subsequent read requests targeting the same device. In this paper, we propose a rank idle time prediction driven last-level cache writeback technique. This technique uses a rank idle time predictor to predict long phases of idle rank cycles. The scheduled dirty cache blocks generated from last-level cache are written back during the predicted long idle rank period. This technique allows servicing write request at the point that minimize the delay it caused to the following read requests. Write-induced interference can be significantly reduced by using our technique.

We evaluate our technique using cycle-accurate full-system simulator and SPEC CPU2006 benchmarks. The results shows the technique improves performance in an eight-core system with memory-intensive workloads on average by 10.5% and 10.1% over conventional writeback using two-rank and four-rank DRAM configurations respectively.

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Cited By

Zhong XZhou XLuo GHuang YWu YCao RTian CPeng J(2023)Soil mineral nitrogen, soil urease activity, nitrogen losses and nitrogen footprint under machine-planted rice with side-deep fertilizationPlant and Soil10.1007/s11104-023-06263-5494:1-2(185-202)Online publication date: 12-Sep-2023
https://doi.org/10.1007/s11104-023-06263-5
Bostanci FOlgun AOrosa LYaglikci AKim JHassan HErgin OMutlu O(2022)DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00087(1141-1155)Online publication date: Apr-2022
https://doi.org/10.1109/HPCA53966.2022.00087
Chaudhuri MGaur JSubramoney S(2019)Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00022(109-118)Online publication date: Nov-2019
https://doi.org/10.1109/ICCD46524.2019.00022
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Index Terms

Rank idle time prediction driven last-level cache writeback
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory
2. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Memory management
        Garbage collection

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cover image ACM Conferences

MSPC '12: Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness

June 2012

82 pages

ISBN:9781450312196

DOI:10.1145/2247684

General Chair:
Lixin Zhang
ICT, Chinese Academy of Sciences
,
Program Chair:
Onur Mutlu
Carnegie Mellon University

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGPLAN: ACM Special Interest Group on Programming Languages

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 June 2012

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PLDI '12

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SIGPLAN

PLDI '12: ACM SIGPLAN Conference on Programming Language Design and Implementation

June 16, 2012

Beijing, China

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Overall Acceptance Rate 6 of 20 submissions, 30%

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Cited By

Zhong XZhou XLuo GHuang YWu YCao RTian CPeng J(2023)Soil mineral nitrogen, soil urease activity, nitrogen losses and nitrogen footprint under machine-planted rice with side-deep fertilizationPlant and Soil10.1007/s11104-023-06263-5494:1-2(185-202)Online publication date: 12-Sep-2023
https://doi.org/10.1007/s11104-023-06263-5
Bostanci FOlgun AOrosa LYaglikci AKim JHassan HErgin OMutlu O(2022)DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00087(1141-1155)Online publication date: Apr-2022
https://doi.org/10.1109/HPCA53966.2022.00087
Chaudhuri MGaur JSubramoney S(2019)Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00022(109-118)Online publication date: Nov-2019
https://doi.org/10.1109/ICCD46524.2019.00022
Lei Li Wei Zhang Huiyao An Xing Zhang (2014)Management of the last level cache for multimedia application system2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)10.1109/ICSICT.2014.7021348(1-4)Online publication date: Oct-2014
https://doi.org/10.1109/ICSICT.2014.7021348

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