research-article

High-performance low-energy STT MRAM based on balanced write scheme

Authors:

Sumeet Kumar Gupta,

Kaushik RoyAuthors Info & Claims

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Pages 9 - 14

https://doi.org/10.1145/2333660.2333665

Published: 30 July 2012 Publication History

Abstract

It is well known that high write time/energy in STT MRAM are aggravated by the asymmetry in write currents for '0'→'1' and '1'→'0' transitions. This asymmetry is primarily due to the source degeneration of the access transistor during write. In this work, we propose a design methodology which avoids the source degeneration of the access transistor, leading to balanced switching times for '0'→'1' and '1'→'0' transitions.

This is achieved by using an additional (negative) bit-line voltage and reduced word-line voltage. The proposed method reduces write time (by ~40%) and write energy (by 65%), enhances reliability of MTJ, and significantly improves tolerance to process variation. In the proposed scheme, source-line can be directly connected to ground signal leading to a compact cell layout.

References

[1]

Berkeley BSIM Group. Berkeley Short-Channel IGFET Model. www-device.eecs.berkeley.edu/bsim/, 2012.

[2]

S. Chatterjee et al. A scalable design methodology for energy minimization of STTRAM: a circuit and architecture perspective. IEEE Trans. VLSI, 19(5):809--817, May 2011.

Digital Library

[3]

X. Fong et al. KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells. In Proc. SISPAD, pages 51--54, Sep. 2011.

[4]

S. Gupta, S. Park, N. Mojumder, and K. Roy. Layout-aware optimization of STT MRAMs. In DATE, 2012.

[5]

F. Hamzaoglu et al. A 3.8GHz 153Mb SRAM design with dynamic stability enhancement and leakage reduction in 45nm high-k metal gate CMOS technology. IEEE J. Solid-State Circuits, 44(1):148--154, Jan. 2009.

[6]

F. Ishihara, F. Sheikh, and B. Nikolic. Level conversion for dual-supply systems. IEEE Trans. VLSI, 12(2):185--195, Feb. 2004.

Digital Library

[7]

K. J. Lee, O. Redon, and B. Dieny. Analytical investigation of spin-transfer dynamics using a perpendicular-to-plane polarizer. Appl. Phys. Lett., 86:022505-1-022505-3, 2005.

[8]

J. Li, P. Ndai, A. Goel, S. Salahuddin, and K. Roy. Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective. IEEE Trans. VLSI, 18(12):1710--1723, Dec. 2010.

Digital Library

[9]

C. J. Lin et al. 45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell. In IEEE IEDM Dig. Tech., pages 279--282, Dec. 2009.

[10]

A. Nigam et al. Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM). In Proc. ISLPED, pages 121--126, Aug. 2011.

Digital Library

[11]

G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen. A novel architecture of the 3D stacked MRAM L2 cache for CMPs. In Proc. IEEE HPCA, pages 239--249, Feb. 2009.

[12]

M. Togo, K. Noda, and T. Tanigawa. Multiple-thickness gate oxide and dual-gate technologies for high-performance logic-embedded DRAMs. In IEEE IEDM Dig. Tech., pages 347--350, Dec. 1998.

[13]

S. Wolf et al. The promise of nanomagnetics and spintronics for future logic and universal memory. Proceedings of the IEEE, 98(12):2155--2168, Dec. 2010.

[14]

E. Wu and E. Nowak. Voltage-splitting technique for reliability evaluation of off-state mode of MOSFETs in ultrathin gate oxides. IEEE Electron Devices Lett., 25(6):414--416, Jun. 2004.

[15]

P. Zhou, B. Zhao, J. Yang, and Y. Zhang. Energy reduction for STT-RAM using early write termination. In Proc. IEEE ICCAD, pages 264--268, Nov. 2009.

Digital Library

Cited By

Ohara RFukunaga ATaichi MKabuto MHamabe RIkegawa MIzumi SKawaguchi H(2024)A Case Study for Improving Performances of Deep-Learning Processor with MRAMIPSJ Transactions on System and LSI Design Methodology10.2197/ipsjtsldm.17.717(7-15)Online publication date: 2024
https://doi.org/10.2197/ipsjtsldm.17.7
Singh RVerma SMittal S(2022)FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance EnhancementIEEE Transactions on Electron Devices10.1109/TED.2022.321720669:12(6699-6704)Online publication date: Dec-2022
https://doi.org/10.1109/TED.2022.3217206
Krautter JMayahinia MGnad DTahoori M(2022)Data Leakage through Self-Terminated Write Schemes in Memristive Caches2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC52403.2022.9712492(666-671)Online publication date: 17-Jan-2022
https://doi.org/10.1109/ASP-DAC52403.2022.9712492
Show More Cited By

Index Terms

High-performance low-energy STT MRAM based on balanced write scheme
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation

Recommendations

Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture
DAC '12: Proceedings of the 49th Annual Design Automation Conference

Spin-transfer torque magnetic RAM (STT MRAM) has emerged as a promising candidate for on-chip memory in future computing platforms. We present a cross-layer (device-circuit-architecture) approach to energy-efficient cache design using STT MRAM. At the ...
Write-optimized reliable design of STT MRAM
ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is ...
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
DAC '09: Proceedings of the 46th Annual Design Automation Conference

This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic tunneling junction (MTJ) write current threshold variability. In ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

July 2012

438 pages

ISBN:9781450312493

DOI:10.1145/2333660

General Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign, USA
,
Massimo Poncino
Politecnico di Torino, Italy
,
Program Chairs:
Pai H. Chou
University of California, Irvine / NTHU
,
Ajith Amerasekera
Texas Instruments, USA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 July 2012

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ISLPED'12

Sponsor:

SIGDA

ISLPED'12: International Symposium on Low Power Electronics and Design

July 30 - August 1, 2012

California, Redondo Beach, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

48
Total Citations
View Citations
1,005
Total Downloads

Downloads (Last 12 months)44
Downloads (Last 6 weeks)4

Reflects downloads up to 28 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Ohara RFukunaga ATaichi MKabuto MHamabe RIkegawa MIzumi SKawaguchi H(2024)A Case Study for Improving Performances of Deep-Learning Processor with MRAMIPSJ Transactions on System and LSI Design Methodology10.2197/ipsjtsldm.17.717(7-15)Online publication date: 2024
https://doi.org/10.2197/ipsjtsldm.17.7
Singh RVerma SMittal S(2022)FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance EnhancementIEEE Transactions on Electron Devices10.1109/TED.2022.321720669:12(6699-6704)Online publication date: Dec-2022
https://doi.org/10.1109/TED.2022.3217206
Krautter JMayahinia MGnad DTahoori M(2022)Data Leakage through Self-Terminated Write Schemes in Memristive Caches2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC52403.2022.9712492(666-671)Online publication date: 17-Jan-2022
https://doi.org/10.1109/ASP-DAC52403.2022.9712492
Kim YChen YLee YPeng LHong S(2022)Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM CachesIEEE Access10.1109/ACCESS.2022.315849310(29419-29431)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3158493
Khan MBhasin SLiu BYuan AChattopadhyay AGhosh S(2021)Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile MemoriesJournal of Low Power Electronics and Applications10.3390/jlpea1104003811:4(38)Online publication date: 28-Sep-2021
https://doi.org/10.3390/jlpea11040038
Nagarajan KAhmed FKhan MDe AChowdhury MGhosh S(2021)SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVMIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.308773429:8(1518-1528)Online publication date: Aug-2021
https://doi.org/10.1109/TVLSI.2021.3087734
Wu LRao STaouil MMedeiros GFieback MMarinissen EKar GHamdioui S(2021)Defect and Fault Modeling Framework for STT-MRAM TestingIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2019.29603759:2(707-723)Online publication date: 1-Apr-2021
https://doi.org/10.1109/TETC.2019.2960375
Wu LRao STaouil MMarinissen EKar GHamdioui S(2021)Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMsIEEE Transactions on Computers10.1109/TC.2021.3125228(1-1)Online publication date: 2021
https://doi.org/10.1109/TC.2021.3125228
Nair SBishnoi RTahoori M(2020)Mitigating Read Failures in STT-MRAM2020 IEEE 38th VLSI Test Symposium (VTS)10.1109/VTS48691.2020.9107605(1-6)Online publication date: Apr-2020
https://doi.org/10.1109/VTS48691.2020.9107605
Hosseini Monazzah ARahmani AMiele ADutt N(2020)CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of ApproximationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.298632039:12(4385-4398)Online publication date: Dec-2020
https://doi.org/10.1109/TCAD.2020.2986320
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten