research-article

Design benchmarking to 7nm with FinFET predictive technology models

Authors:

Yu CaoAuthors Info & Claims

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Pages 15 - 20

https://doi.org/10.1145/2333660.2333666

Published: 30 July 2012 Publication History

Abstract

The coming ten years promise great changes in silicon technology, with the end of planar bulk CMOS and the rise of interconnect parasitics to true significance. With such shifts in the underlying technology, the simple extrapolation of performance metrics may lead to pronounced prediction errors in design pathfinding. In this work, we utilize newly developed Predictive Technology Models for FinFETs aligned to the 2011 ITRS. Together with predictive interconnect models, we project performance and power landscape for the technology nodes from 20nm to 7nm. We present an overview of models, assess the advantage of FinFET over bulk CMOS devices, benchmark the scaling of critical design metrics, and illustrate major design barriers toward the 7nm node.

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Cited By

Sangeeta Mangesh Saini ANarula VCecil K(2025)Leveraging 7-nm FinFET Technology for 1-Bit Full Adder Design: Comprehensive Analysis for Smart ApplicationsRussian Microelectronics10.1134/S106373972460079153:S1(S47-S53)Online publication date: 4-Mar-2025
https://doi.org/10.1134/S1063739724600791
kumari B.S PSaxena D(2024)Design and Analysis of Ultra-low Power Voltage Controlled Oscillator in Nanoscale TechnologiesInternational Journal of Electrical and Electronics Research10.37391/IJEER.12010312:1(12-19)Online publication date: 15-Jan-2024
https://doi.org/10.37391/IJEER.120103
Wu FTian HShen YHou ZRen JGou GSun YYang YRen T(2022)Vertical MoS2 transistors with sub-1-nm gate lengthsNature10.1038/s41586-021-04323-3603:7900(259-264)Online publication date: 9-Mar-2022
https://doi.org/10.1038/s41586-021-04323-3
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Index Terms

Design benchmarking to 7nm with FinFET predictive technology models
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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Published In

cover image ACM Conferences

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

July 2012

438 pages

ISBN:9781450312493

DOI:10.1145/2333660

General Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign, USA
,
Massimo Poncino
Politecnico di Torino, Italy
,
Program Chairs:
Pai H. Chou
University of California, Irvine / NTHU
,
Ajith Amerasekera
Texas Instruments, USA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 July 2012

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ISLPED'12

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ISLPED'12: International Symposium on Low Power Electronics and Design

July 30 - August 1, 2012

California, Redondo Beach, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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https://doi.org/10.1134/S1063739724600791
kumari B.S PSaxena D(2024)Design and Analysis of Ultra-low Power Voltage Controlled Oscillator in Nanoscale TechnologiesInternational Journal of Electrical and Electronics Research10.37391/IJEER.12010312:1(12-19)Online publication date: 15-Jan-2024
https://doi.org/10.37391/IJEER.120103
Wu FTian HShen YHou ZRen JGou GSun YYang YRen T(2022)Vertical MoS2 transistors with sub-1-nm gate lengthsNature10.1038/s41586-021-04323-3603:7900(259-264)Online publication date: 9-Mar-2022
https://doi.org/10.1038/s41586-021-04323-3
HATTORI NSHIOMI JMASUDA YISHIHARA TSHINYA ANOTOMI M(2021)Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic ActivationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2020KEP0016E104.A:11(1477-1487)Online publication date: 1-Nov-2021
https://doi.org/10.1587/transfun.2020KEP0016
Haq SSharma V(2021)Challenges in Low Power VLSI Design: A Review2021 5th International Conference on Electronics, Communication and Aerospace Technology (ICECA)10.1109/ICECA52323.2021.9676055(191-195)Online publication date: 2-Dec-2021
https://doi.org/10.1109/ICECA52323.2021.9676055
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Yasir MAnsari M(2020)Performance Investigation of FinFET-Based MO-CCII and its Applications: Resistor-Less Multi-Function Bi-Quadratic Filter and Balanced ModulatorJournal of Circuits, Systems and Computers10.1142/S021812662050175329:11(2050175)Online publication date: 21-Jan-2020
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Hyun DShin Y(2019)Integrated Approach of Airgap Insertion for Circuit Timing OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/330649424:2(1-22)Online publication date: 14-Feb-2019
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Ishihara TShiomi JHattori NMasuda YShinya ANotomi M(2019)An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator2019 IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, Information and Computing Systems (PHOTONICS)10.1109/PHOTONICS49561.2019.00008(15-21)Online publication date: Nov-2019
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