skip to main content
10.1145/2333660.2333680acmconferencesArticle/Chapter ViewAbstractPublication PagesislpedConference Proceedingsconference-collections
abstract

An ARM perspective on addressing low-power energy-efficient SoC designs

Published: 30 July 2012 Publication History

Abstract

In this paper the lessons learned as an IP provider addressing the transfer of low power designs and implementation flows and methodologies into energy-efficient System-on-Chip products are discussed, followed by a preview of the more promising techniques for future deployment.

References

[1]
Mudge, Trevor, "Power: A First Class Architectural Design Constraint" IEEE Computer, vol. 34, no. 4, April 2001. http://doi.ieeecomputersociety.org/10.1109/2.917539
[2]
Keating, M., Flynn, D. et al, "Low Power Methodology Manual - for System-on-Chip Design", Springer 2007 ISBN: 978-0-387-71818-7 http://www.lpmm-book.org/
[3]
Shi, K. Flynn, D. "Power Gating Design Tradeoffs and Considerations in Production Low-Power Designs", DesignCon 2009 http://www.designcon.com/infovault/paper.asp?PAPER_ID=474
[4]
Mutoh S. et al. "A 1v multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone applications" ISSCC1996, pages 168--169, 1996.
[5]
Flynn, D. Gibbons, A. "Design for State Retention: Strategies and Case Studies" SNUG San Jose 2008, Track TA2.
[6]
Accellera UPF Standard version 1.0, February 2007, now part of IEEE standard 1801 http://www.accellera.org/activities/p1801_upf
[7]
Si2 Common Power Format, CPF, specification http://www.si2.org/?page=811
[8]
1801--2009 IEEE Standard for Design and Verification of Low Power Integrated Circuits http://standards.ieee.org/develop/wg/UPF.html http://standards.ieee.org/findstds/standard/1801-2009.html
[9]
Stan, M., "Low-Threshold CMOS Circuits with Low Standby Current," in Proceedings of the International Symposium on Low-Power Electronics and Design. Monterey, CA: IEEE/ACM, 1998, pp. 97--99.
[10]
Mistry, J., et al, "Sub-clock Power-Gating Technique for Minimizing Leakage Power during Active Mode", DATE 2011 http://eprints.ecs.soton.ac.uk/21768/
[11]
EUROPRACTICE mini@sic programme: http://www.europractice-ic.com/prototyping_minisic.php

Cited By

View all
  • (2020) Autonomous Power Management With Double- Q Reinforcement Learning Method IEEE Transactions on Industrial Informatics10.1109/TII.2019.295393216:3(1938-1946)Online publication date: Mar-2020
  • (2017)Machine learning for run-time energy optimisation in many-core systemsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130749(1592-1596)Online publication date: 27-Mar-2017
  • (2016)Learning Transfer-Based Adaptive Energy Minimization in Embedded SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.248186735:6(877-890)Online publication date: Jun-2016
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
July 2012
438 pages
ISBN:9781450312493
DOI:10.1145/2333660
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 July 2012

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. automatic test pattern generation (atpg)
  2. central processor unit (cpu)
  3. dynamic voltage and frequency scaling (dvfs)
  4. eco-system
  5. electronic design automation (eda)
  6. energy-efficiency
  7. implementation ip (iip)
  8. intellectual property (ip)
  9. ip-deployment
  10. logical ip (lip)
  11. low-power
  12. multi-threshold cmos (mtcmos)
  13. multi-voltage (mv)
  14. physical ip (pip)
  15. power intent
  16. power-gating (pg)
  17. standard-cell
  18. state-retention (sr)
  19. system-on-chip (soc)

Qualifiers

  • Abstract

Conference

ISLPED'12
Sponsor:
ISLPED'12: International Symposium on Low Power Electronics and Design
July 30 - August 1, 2012
California, Redondo Beach, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)6
  • Downloads (Last 6 weeks)1
Reflects downloads up to 21 Jan 2025

Other Metrics

Citations

Cited By

View all
  • (2020) Autonomous Power Management With Double- Q Reinforcement Learning Method IEEE Transactions on Industrial Informatics10.1109/TII.2019.295393216:3(1938-1946)Online publication date: Mar-2020
  • (2017)Machine learning for run-time energy optimisation in many-core systemsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130749(1592-1596)Online publication date: 27-Mar-2017
  • (2016)Learning Transfer-Based Adaptive Energy Minimization in Embedded SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.248186735:6(877-890)Online publication date: Jun-2016
  • (2015)Adaptive energy minimization of embedded heterogeneous systems using regression-based learning2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2015.7347594(103-110)Online publication date: Sep-2015
  • (2015)Power-aware multi-voltage custom memory models for enhancing RTL and low power verificationProceedings of the 2015 33rd IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2015.7357080(24-31)Online publication date: 18-Oct-2015
  • (2014)Device and technology implications of the Internet of Things2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers10.1109/VLSIT.2014.6894339(1-4)Online publication date: Jun-2014
  • (2013)Smart Everything: Will Intelligent Systems Reduce Resource Use?Annual Review of Environment and Resources10.1146/annurev-environ-021512-11054938:1(311-343)Online publication date: 17-Oct-2013
  • (2013)Power gating applied to MP-SoCs for standby-mode power managementProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488930(1-5)Online publication date: 29-May-2013
  • (2013)Power Gating and State Retention Applied to SOC Standby Power ManagementFrequency References, Power Management for SoC, and Smart Wireless Interfaces10.1007/978-3-319-01080-9_12(209-226)Online publication date: 1-Aug-2013

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media