Eric Donkoh
ABSTRACT
A register file is presented that uses an unclocked wordline with dynamic bitline sub-segmentation and stack-forcing to reduce both active and standby leakage. The proposed technique improves scalability to a larger number of entries per local bitline segment. For an example 32nm-CMOS 4-write, 6-read port 32 bits x 168 entries register file, the proposed bitline segmentation technique improves local bitline delay by 33%, lowers standby leakage by 70%, and reduces the number of clocked wordlines by 83% when compared with a conventional design. Furthermore, wordline sharing is shown to reduce the number of wordlines by as much as 58%.
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Cross Ref
- E. Donkoh et al. "Register File Write Data Gating Techniques and Break-Even Analysis Model" ISLPED 2012. Google ScholarDigital Library
- P. Packan et. al.,"High Performance 32nm Logic Technology Featuring 2nd Generation High-k + Metal Gate Transistors," IEDM 2009, pp 1--4.Google Scholar
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- S. Narendra, et al, "Scaling of Stack Effect and its Application for Leakage Reduction", ISLPED, 2001 Google ScholarDigital Library
- R. Kumar and G. Hinton, "A family of 45nm IA processors," ISSCC'09 Digest of Tech. Papers, pp. 58--59.Google Scholar
Index Terms
- A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalability
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