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Static and dynamic co-optimizations for blocks mapping in hybrid caches

Published: 30 July 2012 Publication History

Abstract

In this paper, a combined static and dynamic scheme is proposed to optimize the block placement for endurance and energy-efficiency in a hybrid SRAM and STT-RAM cache. With the proposed scheme, STT-RAM endurance is maximized while performance is maintained. We use the compiler to provide static hints to guide initial data placement, and use the hardware to correct the hints based on the run-time cache behavior. Experimental results show that the combined scheme improves the endurance by 23.9x and 5.9x compared to pure static and pure dynamic optimizations respectively. Furthermore, the system energy can be reduced by 17% compared to pure dynamic optimization through minimizing STT-RAM writes.

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  • (2020)A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)10.1109/VLSI-SOC46417.2020.9344087(94-99)Online publication date: 5-Oct-2020
  • (2020)Statistical Behavior Guided Block Allocation in Hybrid Cache-Based Edge Computing for Cyber-Physical-Social SystemsIEEE Access10.1109/ACCESS.2020.29723058(29055-29063)Online publication date: 2020
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    cover image ACM Conferences
    ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
    July 2012
    438 pages
    ISBN:9781450312493
    DOI:10.1145/2333660
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 30 July 2012

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    Author Tags

    1. endurance
    2. energy
    3. hybrid cache
    4. l2 cache
    5. stt-ram

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    ISLPED'12
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    ISLPED'12: International Symposium on Low Power Electronics and Design
    July 30 - August 1, 2012
    California, Redondo Beach, USA

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    Overall Acceptance Rate 398 of 1,159 submissions, 34%

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    • (2020)A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)10.1109/VLSI-SOC46417.2020.9344087(94-99)Online publication date: 5-Oct-2020
    • (2020)Statistical Behavior Guided Block Allocation in Hybrid Cache-Based Edge Computing for Cyber-Physical-Social SystemsIEEE Access10.1109/ACCESS.2020.29723058(29055-29063)Online publication date: 2020
    • (2020)Integer linear programming model for allocation and migration of data blocks in the STT-RAM-based hybrid cachesIET Computers & Digital Techniques10.1049/iet-cdt.2019.0070Online publication date: 7-Jan-2020
    • (2019)Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache DesignACM Transactions on Design Automation of Electronic Systems10.1145/332169324:4(1-25)Online publication date: 29-May-2019
    • (2019)per-Operation Reusability based Allocation and Migration Policy for Hybrid CacheIEEE Transactions on Computers10.1109/TC.2019.2944163(1-1)Online publication date: 2019
    • (2019)TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and MigrationIEEE Transactions on Computers10.1109/TC.2019.291720868:12(1704-1719)Online publication date: 1-Dec-2019
    • (2018)BenzeneACM Transactions on Architecture and Code Optimization10.1145/317796315:1(1-23)Online publication date: 22-Mar-2018
    • (2018)Performance and Power-Efficient Design of Dense Non-Volatile Cache in CMPsIEEE Transactions on Computers10.1109/TC.2018.279606767:7(1054-1061)Online publication date: 1-Jul-2018
    • (2018)SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU---GPU heterogeneous architecturesThe Journal of Supercomputing10.1007/s11227-018-2389-374:7(3388-3414)Online publication date: 1-Jul-2018
    • (2016)LAPACM SIGARCH Computer Architecture News10.1145/3007787.300114844:3(103-114)Online publication date: 18-Jun-2016
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