poster

Design space exploration of workload-specific last-level caches

Authors:

Karthik Swaminathan,

Emre Kultursay,

Vinay Saripalli,

Vijaykrishnan Narayanan,

Mahmut KandemirAuthors Info & Claims

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Pages 243 - 248

https://doi.org/10.1145/2333660.2333718

Published: 30 July 2012 Publication History

Abstract

Leakage power of last-level caches constitute a significant part of overall power consumption. Various circuit-level and technology-based methods have been proposed to reduce cache leakage. However, from a system designer's perspective, for a particular configuration and workload, it is not clear which method will be most effective. In this work, we make a detailed evaluation and comparison of cache energy reduction techniques. Our results show that when energy is very scarce and important, the best results are obtained with highly energy efficient Tunnel-FET caches. When the available energy increases and performance becomes a bigger concern, there is no single winner. While a small number of capacity sensitive workloads benefit from increased capacity of STT-RAM caches, latency sensitive workloads prefer solutions with smaller latency penalties such as drowsy caches.

References

[1]

ITRS Emerging Research Devices (ERD) Chapter. In ITRS, 2011.

[2]

Process Integration, Devices, and Structures (PIDS). In ITRS, 2011.

[3]

X. Dong et al. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Non-Volatile Memory. In TCAD, Dec. 2011.

[4]

K. Flautner et al. Drowsy caches: simple techniques for reducing leakage power. In ISCA, 2002.

Digital Library

[5]

M. R. Guthaus et al. MiBench: A free, commercially representative embedded benchmark suite. In WWC, 2001.

Digital Library

[6]

J. L. Henning. SPEC CPU2006 benchmark descriptions. SIGARCH Comput. Archit. News, 34(4), Sep 2006.

Digital Library

[7]

M. Hosomi et al. A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM. In IEDM, 2005.

[8]

T. Kawahara et al. 2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. JSSC, 43, Jan. 2008.

[9]

N. S. Kim et al. Circuit and microarchitectural techniques for reducing cache leakage power. TVLSI, 12(2), Feb. 2004.

Digital Library

[10]

J. Kin et al. The filter cache: an energy efficient memory structure. In MICRO, 1997.

Digital Library

[11]

J. P. Kulkarni et al. A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM. In ISLPED, 2007.

Digital Library

[12]

A. K. Mishra et al. Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. In ISCA, 2011.

Digital Library

[13]

S. Mookerjea et al. Experimental demonstration of 100nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications. In IEDM, 2009.

[14]

N. Muralimanohar et al. Architecting Efficient Interconnects for Large Caches with CACTI 6.0. IEEE Micro, 28(1), Jan. 2008.

Digital Library

[15]

S. Mutoh et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. JSSC, 30(8):847--854, Aug 1995.

[16]

H. Qin et al. SRAM leakage suppression by minimizing standby supply voltage. In ISQED, 2004.

Digital Library

[17]

V. Saripalli et al. Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design. NanoArch, 2011.

Digital Library

[18]

L. Shifren. Leakage power, it's worse than you think. In EE Times, 2011.

[19]

S. Srikantaiah et al. MorphCache: A reconfigurable adaptive multi-level cache hierarchy. In HPCA, 2011.

Digital Library

[20]

K. Swaminathan et al. Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores. In ISLPED, 2011.

Digital Library

[21]

Synopsys. TCAD Sentaurus Device Manual, Release: C-2009.06, 2009.

[22]

W. Wong et al. VOSCH: Voltage scaled cache hierarchies. In ICCD, 2007.

[23]

B. Zhai et al. A sub-200mV 6T-SRAM in 0.13um CMOS. In ISSCC, 2007.

Cited By

Mittal SVetter J(2016)EqualWrites: Reducing Intra-Set Write Variations for Enhancing Lifetime of Non-Volatile CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.238911324:1(103-114)Online publication date: Jan-2016
https://doi.org/10.1109/TVLSI.2015.2389113
Cheng HPoremba MShahidi NStalev IIrwin MKandemir MSampson JXie Y(2015)EECacheACM Transactions on Architecture and Code Optimization10.1145/275655212:2(1-22)Online publication date: 8-Jul-2015
https://dl.acm.org/doi/10.1145/2756552
Min SJavaid HParameswaran S(2013)XDRAProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488761(1-10)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488761

Index Terms

Design space exploration of workload-specific last-level caches
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Information & Contributors

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Published In

cover image ACM Conferences

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

July 2012

438 pages

ISBN:9781450312493

DOI:10.1145/2333660

General Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign, USA
,
Massimo Poncino
Politecnico di Torino, Italy
,
Program Chairs:
Pai H. Chou
University of California, Irvine / NTHU
,
Ajith Amerasekera
Texas Instruments, USA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 30 July 2012

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ISLPED'12

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SIGDA

ISLPED'12: International Symposium on Low Power Electronics and Design

July 30 - August 1, 2012

California, Redondo Beach, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Mittal SVetter J(2016)EqualWrites: Reducing Intra-Set Write Variations for Enhancing Lifetime of Non-Volatile CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.238911324:1(103-114)Online publication date: Jan-2016
https://doi.org/10.1109/TVLSI.2015.2389113
Cheng HPoremba MShahidi NStalev IIrwin MKandemir MSampson JXie Y(2015)EECacheACM Transactions on Architecture and Code Optimization10.1145/275655212:2(1-22)Online publication date: 8-Jul-2015
https://dl.acm.org/doi/10.1145/2756552
Min SJavaid HParameswaran S(2013)XDRAProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488761(1-10)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488761

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