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Designing for dark silicon: a methodological perspective on energy efficient systems

Authors:

Jason Allred,

Sanghamitra Roy,

Koushik ChakrabortyAuthors Info & Claims

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Pages 255 - 260

https://doi.org/10.1145/2333660.2333720

Published: 30 July 2012 Publication History

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Abstract

The emergence of dark silicon - a fundamental design constraint absent in the past generations - brings intriguing challenges and opportunities in microprocessor design. To gracefully embrace dark silicon, design methodologies must adapt themselves to identify progressive systems that can effectively exploit the growing dark silicon. We demonstrate that relying on traditional design metrics may lead to sub-optimal design choices with the rise of the dark silicon area. We provide a new metric to guide a dark silicon aware system design and propose a stochastic optimization algorithm for dark silicon aware multicore system design. Our design approach shows 7-23% benefit in upcoming technology generations.

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Cited By

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Kulkarni AMahajan S(2022)Improving Effectiveness of Parallel Processing with Smart Cache Utilization for Energy Saving and Temperature Reduction In Chip Multiprocessors2022 IEEE 4th International Conference on Cybernetics, Cognition and Machine Learning Applications (ICCCMLA)10.1109/ICCCMLA56841.2022.9989285(128-132)Online publication date: 8-Oct-2022
https://doi.org/10.1109/ICCCMLA56841.2022.9989285
Lee WKang TLee JHan KKim JPedram M(2019)TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power MethodsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285924038:9(1758-1770)Online publication date: Sep-2019
https://doi.org/10.1109/TCAD.2018.2859240
AL-Obaidy FAsad AMohammadi F(2019)Reconfigurable Hybrid Cache Hierarchy in 3D Chip-Multi Processors Based on a Convex optimization Method2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)10.1109/CCECE.2019.8861876(1-6)Online publication date: May-2019
https://doi.org/10.1109/CCECE.2019.8861876
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Index Terms

Designing for dark silicon: a methodological perspective on energy efficient systems
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
      2. Self-organizing autonomic computing

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Published In

ISLPED '12: Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

July 2012

438 pages

ISBN:9781450312493

DOI:10.1145/2333660

General Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign, USA
,
Massimo Poncino
Politecnico di Torino, Italy
,
Program Chairs:
Pai H. Chou
University of California, Irvine / NTHU
,
Ajith Amerasekera
Texas Instruments, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 30 July 2012

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ISLPED'12: International Symposium on Low Power Electronics and Design

July 30 - August 1, 2012

California, Redondo Beach, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Kulkarni AMahajan S(2022)Improving Effectiveness of Parallel Processing with Smart Cache Utilization for Energy Saving and Temperature Reduction In Chip Multiprocessors2022 IEEE 4th International Conference on Cybernetics, Cognition and Machine Learning Applications (ICCCMLA)10.1109/ICCCMLA56841.2022.9989285(128-132)Online publication date: 8-Oct-2022
https://doi.org/10.1109/ICCCMLA56841.2022.9989285
Lee WKang TLee JHan KKim JPedram M(2019)TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power MethodsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285924038:9(1758-1770)Online publication date: Sep-2019
https://doi.org/10.1109/TCAD.2018.2859240
AL-Obaidy FAsad AMohammadi F(2019)Reconfigurable Hybrid Cache Hierarchy in 3D Chip-Multi Processors Based on a Convex optimization Method2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)10.1109/CCECE.2019.8861876(1-6)Online publication date: May-2019
https://doi.org/10.1109/CCECE.2019.8861876
Kapadia NPasricha S(2017)A Runtime Framework for Robust Application Scheduling With Adaptive Parallelism in the Dark-Silicon EraIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.259423825:2(534-546)Online publication date: 1-Feb-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2594238
Raparti VKapadia NPasricha S(2017)ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-Based Chip MultiprocessorsIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2017.26868563:2(72-85)Online publication date: 1-Apr-2017
https://doi.org/10.1109/TMSCS.2017.2686856
Shafique MGarg S(2017)Computing in the Dark Silicon Era: Current Trends and Research ChallengesIEEE Design & Test10.1109/MDAT.2016.263340834:2(8-23)Online publication date: Apr-2017
https://doi.org/10.1109/MDAT.2016.2633408
Yang LLiu WGuan NLi MChen PSha E(2017)Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2017.7858371(494-499)Online publication date: Jan-2017
https://doi.org/10.1109/ASPDAC.2017.7858371
Yang LLiu WJiang WChen CLi MChen PSha E(2017)Hardware-software collaboration for dark silicon heterogeneous many-core systemsFuture Generation Computer Systems10.1016/j.future.2016.09.01268(234-247)Online publication date: Mar-2017
https://doi.org/10.1016/j.future.2016.09.012
Khan MShafique MHenkel JKhan MShafique MHenkel J(2017)Background and Related WorkEnergy Efficient Embedded Video Processing Systems10.1007/978-3-319-61455-7_2(25-65)Online publication date: 19-Sep-2017
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Kapadia NPasricha S(2017)Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore SystemsThe Dark Side of Silicon10.1007/978-3-319-31596-6_8(217-236)Online publication date: 1-Jan-2017
https://doi.org/10.1007/978-3-319-31596-6_8
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Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse

A Landscape of the New Dark Silicon Design Regime

Exploring Energy Scalability in Coprocessor-Dominated Architectures for Dark Silicon

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