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Hardware-software co-design of AES on FPGA

Authors:

Saambhavi Baskaran,

Pachamuthu RajalakshmiAuthors Info & Claims

ICACCI '12: Proceedings of the International Conference on Advances in Computing, Communications and Informatics

Pages 1118 - 1122

https://doi.org/10.1145/2345396.2345575

Published: 03 August 2012 Publication History

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Abstract

This paper presents a compact hardware-software co-design of Advanced Encryption Standard (AES) on the field programmable gate arrays (FPGA) designed for low-cost embedded systems. The design uses MicroBlaze, a soft-core processor from Xilinx. The computationally intensive operations of the AES are implemented in hardware for better speed. The sub-byte calculation is designed with the help of the processor carrying out the calculations using hardware blocks implemented using FPGA. By incorporating the processor in the AES design, the total number of slices required to implement the AES algorithm on FPGA is proved to be reduced. The entire AES system design is validated using 460 slices in Spartan-3E XC3S500E, which is one of the low-cost FPGAs.

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Neal ZGoulart AChennamaneni A(2024)On the Practicality of Hardware Acceleration for Lightweight Block Ciphers2024 IEEE International Workshop Technical Committee on Communications Quality and Reliability (CQR)10.1109/CQR62340.2024.10705892(31-36)Online publication date: 9-Sep-2024
https://doi.org/10.1109/CQR62340.2024.10705892
Peng PMa CGe JGao NTu C(2020)A Hardware/Software Collaborative SM4 Implementation Resistant to Side-channel Attacks on ARM-FPGA Embedded SoC*2020 IEEE Symposium on Computers and Communications (ISCC)10.1109/ISCC50000.2020.9219591(1-7)Online publication date: Jul-2020
https://doi.org/10.1109/ISCC50000.2020.9219591
Mohamed Asan Basiri MShukla S(2019)Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH EncoderVLSI Design and Test10.1007/978-981-13-5950-7_1(3-15)Online publication date: 25-Jan-2019
https://doi.org/10.1007/978-981-13-5950-7_1
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Hardware-software co-design of AES on FPGA
1. Computer systems organization

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ICACCI '12: Proceedings of the International Conference on Advances in Computing, Communications and Informatics

August 2012

1307 pages

ISBN:9781450311960

DOI:10.1145/2345396

Editors:
Sabu M. Thampi,
El-Sayed El-Afry,
Javier Aguiar,
General Chairs:
K. Gopalan
Purdue University Calumet
,
Sabu M. Thampi
Indian Institute of Information Technology and Management - Kerala, India

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 03 August 2012

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ICACCI '12: 2012 International Conference on Advances in Computing, Communications and Informatics

August 3 - 5, 2012

Chennai, India

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Neal ZGoulart AChennamaneni A(2024)On the Practicality of Hardware Acceleration for Lightweight Block Ciphers2024 IEEE International Workshop Technical Committee on Communications Quality and Reliability (CQR)10.1109/CQR62340.2024.10705892(31-36)Online publication date: 9-Sep-2024
https://doi.org/10.1109/CQR62340.2024.10705892
Peng PMa CGe JGao NTu C(2020)A Hardware/Software Collaborative SM4 Implementation Resistant to Side-channel Attacks on ARM-FPGA Embedded SoC*2020 IEEE Symposium on Computers and Communications (ISCC)10.1109/ISCC50000.2020.9219591(1-7)Online publication date: Jul-2020
https://doi.org/10.1109/ISCC50000.2020.9219591
Mohamed Asan Basiri MShukla S(2019)Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH EncoderVLSI Design and Test10.1007/978-981-13-5950-7_1(3-15)Online publication date: 25-Jan-2019
https://doi.org/10.1007/978-981-13-5950-7_1
Cowart RCoe DKulick JMilenković A(2017)An Implementation and Experimental Evaluation of Hardware Accelerated Ciphers in All-Programmable SoCsProceedings of the 2017 ACM Southeast Conference10.1145/3077286.3077297(34-41)Online publication date: 13-Apr-2017
https://dl.acm.org/doi/10.1145/3077286.3077297
Robertazzi TRobertazzi T(2017)AES and Quantum CryptographyIntroduction to Computer Networking10.1007/978-3-319-53103-8_11(129-140)Online publication date: 28-Feb-2017
https://doi.org/10.1007/978-3-319-53103-8_11

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A novel AES-256 implementation on FPGA using co-processor based architecture

Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet

LUT-based FPGA Implementation of SMS4/AES/Camellia

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