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Energy-guided exploration of on-chip network design for exa-scale computing

Published: 03 June 2012 Publication History

Abstract

Designing energy-efficient systems under tight performance and energy constraints becomes increasingly challenging for exascale computing. In particular, interconnecting hundreds of cores, caches, integrated memory and I/O controllers in energy efficient way stands out as a new challenge. This paper proposes hierarchical on-chip networks that take the proximity advantage between the cores in smaller clusters as a promising approach toward energy-efficient high performance computing. The design trade-offs of hierarchical interconnect architectures are studied using a fast and scalable design space exploration tool for exascale systems with number of cores in the order of thousands. In particular, we consider a system with 720 processing nodes and two-level network hierarchy. By supporting both traditional cache-based memory model and scratch pad memory (SPM) model, the target system architecture proves to be a good testbed for energy-guided exploration of hierarchical networks.

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  • (2021)Theoretical Analysis and Evaluation of NoCs with Weighted Round-Robin Arbitration2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643448(1-9)Online publication date: 1-Nov-2021
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cover image ACM Conferences
SLIP '12: Proceedings of the International Workshop on System Level Interconnect Prediction
June 2012
58 pages
ISBN:9781450314374
DOI:10.1145/2347655
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 03 June 2012

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View all
  • (2023)Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite BuffersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.325066231:5(670-683)Online publication date: May-2023
  • (2021)Analytical Performance Modeling of NoCs under Priority Arbitration and Bursty TrafficIEEE Embedded Systems Letters10.1109/LES.2020.301300313:3(98-101)Online publication date: Sep-2021
  • (2021)Theoretical Analysis and Evaluation of NoCs with Weighted Round-Robin Arbitration2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643448(1-9)Online publication date: 1-Nov-2021
  • (2019)Analytical Performance Models for NoCs with Multiple Priority Traffic ClassesACM Transactions on Embedded Computing Systems10.1145/335817618:5s(1-21)Online publication date: 7-Oct-2019

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