ABSTRACT
In a network-on-chip based multicore, an off-chip data access needs to travel through the on-chip network, spending considerable amount of time within the chip (in addition to the memory access itself). Further, it also causes additional delays for on-chip accesses by creating contention on network resources. In this paper, we propose a compiler-guided off-chip data access localization strategy to ensure that, an off-chip access traverses a small number of links (hops) to reach the memory controller which governs the memory bank that holds the requested data. We present an extensive evaluation of this strategy using a set of 12 multithreaded application programs. The results collected clearly emphasize the importance of localizing off-chip accesses.
- V. Aslot et al. SPEComp: A new benchmark suite for measuring parallel computer performance. OpenMP Shared Memory Parallel Programming, 2001. Google ScholarDigital Library
- L. Benini and G. D. Micheli. Networks on Chips: Technology and Tools. Elsevier Inc., 2006.Google Scholar
- C. Kim et al. An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. Proc. of ASPLOS, 2002. Google ScholarDigital Library
- Y. Kim et al. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. Proc. of HPCA, 2010.Google Scholar
- Y. Kim et al. Thread cluster memory scheduling: Exploiting differences in memory access behavior. Proc. of MICRO, 2010. Google ScholarDigital Library
- Q. Lu et al. Data layout transformation for enhancing data locality on NUCA chip multiprocessors. Proc. of PACT, 2009. Google ScholarDigital Library
- S. C. Woo et al. The SPLASH-2 programs: Characterization and methodological considerations. Proc. of ISCA, 1995. Google ScholarDigital Library
- Y. Zhang et al. A data layout optimization framework for NUCA-based multicores. Proc. of MICRO, 2011. Google ScholarDigital Library
Index Terms
- Off-chip access localization for NoC-based multicores
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