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Off-chip access localization for NoC-based multicores

Published: 19 September 2012 Publication History

Abstract

In a network-on-chip based multicore, an off-chip data access needs to travel through the on-chip network, spending considerable amount of time within the chip (in addition to the memory access itself). Further, it also causes additional delays for on-chip accesses by creating contention on network resources. In this paper, we propose a compiler-guided off-chip data access localization strategy to ensure that, an off-chip access traverses a small number of links (hops) to reach the memory controller which governs the memory bank that holds the requested data. We present an extensive evaluation of this strategy using a set of 12 multithreaded application programs. The results collected clearly emphasize the importance of localizing off-chip accesses.

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C. Kim et al. An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. Proc. of ASPLOS, 2002.
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Y. Kim et al. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. Proc. of HPCA, 2010.
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Y. Kim et al. Thread cluster memory scheduling: Exploiting differences in memory access behavior. Proc. of MICRO, 2010.
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Q. Lu et al. Data layout transformation for enhancing data locality on NUCA chip multiprocessors. Proc. of PACT, 2009.
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Y. Zhang et al. A data layout optimization framework for NUCA-based multicores. Proc. of MICRO, 2011.

Cited By

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  • (2014)Quantifying and Optimizing the Impact of Victim Cache Line Selection in Manycore SystemsProceedings of the 2014 IEEE 22nd International Symposium on Modelling, Analysis & Simulation of Computer and Telecommunication Systems10.1109/MASCOTS.2014.54(385-394)Online publication date: 9-Sep-2014

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Published In

cover image ACM Conferences
PACT '12: Proceedings of the 21st international conference on Parallel architectures and compilation techniques
September 2012
512 pages
ISBN:9781450311823
DOI:10.1145/2370816

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 September 2012

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Author Tags

  1. compiler
  2. data locality
  3. memory controller
  4. network-on-chip

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PACT '12
Sponsor:
  • IFIP WG 10.3
  • SIGARCH
  • IEEE CS TCPP
  • IEEE CS TCAA

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Overall Acceptance Rate 121 of 471 submissions, 26%

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Cited By

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  • (2014)Quantifying and Optimizing the Impact of Victim Cache Line Selection in Manycore SystemsProceedings of the 2014 IEEE 22nd International Symposium on Modelling, Analysis & Simulation of Computer and Telecommunication Systems10.1109/MASCOTS.2014.54(385-394)Online publication date: 9-Sep-2014

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