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abstract

Design of a storage processing unit

Published: 19 September 2012 Publication History

Abstract

Researchers showed that performing computation directly on storage devices improves system performance in terms of energy consumption and processing time. For example, Riedel et al. [2] proposed an active disk which performs computation using the processor in a hard disk drive (HDD). Their experimental results showed that the active disk-based system had a factor of 2x performance improvement [2]. However, because the performance gap between the HDDs and CPUs becomes larger and larger, the active disk-based improvement is quite limited. As the role of flash memory increases in storage architectures, solid-state drives (SSDs) have gradually displaced the HDDs with higher access performance and lower power consumption. Researchers also proposed an active flash, which performs computation using a controller in the SSD [1]. However, the SSD controller needs to implement a flash translation layer to make the SSD as an emulated HDD for most operating systems. It also needs to communicate with a host interface to transfer required data. The additional computation power can be utilized is quite limited. To maximize the computation power on the SSD, we propose a processor design called storage processing unit (SPU).

References

[1]
S. Boboila, Y. Kim, S. Vazhkudai, P. Desnoyers, and G. Shipman. Active flash: Out-of-core data analytics on flash storage. In IEEE Symposium on Massive Storage Systems and Technologies (MSST 2011), 2011.
[2]
E. Riedel, C. Faloutsos, and D. F. Nagle. Active disk architecture for databases. Carnegie Mellon University Technical Report Carnegie Mellon University-CS-00-145, May 2000.

Cited By

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  • (2013)The design of bus accessing timing to NAND flash array for high bandwidth2013 International SoC Design Conference (ISOCC)10.1109/ISOCC.2013.6864026(274-277)Online publication date: Nov-2013

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Published In

cover image ACM Conferences
PACT '12: Proceedings of the 21st international conference on Parallel architectures and compilation techniques
September 2012
512 pages
ISBN:9781450311823
DOI:10.1145/2370816

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 September 2012

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Author Tags

  1. memory systems
  2. parallel architectures
  3. solid-state drive

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PACT '12
Sponsor:
  • IFIP WG 10.3
  • SIGARCH
  • IEEE CS TCPP
  • IEEE CS TCAA

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Overall Acceptance Rate 121 of 471 submissions, 26%

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Cited By

View all
  • (2013)The design of bus accessing timing to NAND flash array for high bandwidth2013 International SoC Design Conference (ISOCC)10.1109/ISOCC.2013.6864026(274-277)Online publication date: Nov-2013

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