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Minimizing power supply noise through harmonic mappings in networks-on-chip

Published: 07 October 2012 Publication History

Abstract

Power supply integrity has become a critical concern with the rapid shrinking of device dimensions and the ever increasing power consumption in nano-scale integration. Particularly, power supply noise is strongly correlated to the spatial distribution of activity densities and this can be attributed to the on-chip communication, which dictates the power dissipation and overall system performance in networks-on-chip. In this paper, we propose a new mapping strategy aiming to create a balanced activity distribution across the whole chip. We formulate the problem of application mapping as a minimization of the activity density by employing a repulsive force-based objective function. Metrics of regional activity density and characteristics of its impact on power supply noise are considered. The proposed method has been rigorously evaluated based on a large set of real-application benchmarks. Significant reduction in power supply noise can be achieved with negligible energy overhead. This new approach would provide a more scalable solution for future large-scale system integration.

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  • (2022)Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon EraACM Journal on Emerging Technologies in Computing Systems10.1145/350177118:3(1-18)Online publication date: 22-Mar-2022
  • (2021)Power density aware application mapping in mesh-based network-on-chip architectureIntegration, the VLSI Journal10.1016/j.vlsi.2021.08.00881:C(342-353)Online publication date: 1-Nov-2021
  • (2018)PARMProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196090(1-6)Online publication date: 24-Jun-2018
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      cover image ACM Conferences
      CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
      October 2012
      596 pages
      ISBN:9781450314268
      DOI:10.1145/2380445
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 07 October 2012

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      Author Tags

      1. activity factor
      2. application mapping
      3. networks-on-chip
      4. power density
      5. power supply noise

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      • Research-article

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      ESWEEK'12
      ESWEEK'12: Eighth Embedded System Week
      October 7 - 12, 2012
      Tampere, Finland

      Acceptance Rates

      CODES+ISSS '12 Paper Acceptance Rate 48 of 163 submissions, 29%;
      Overall Acceptance Rate 280 of 864 submissions, 32%

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      Cited By

      View all
      • (2022)Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon EraACM Journal on Emerging Technologies in Computing Systems10.1145/350177118:3(1-18)Online publication date: 22-Mar-2022
      • (2021)Power density aware application mapping in mesh-based network-on-chip architectureIntegration, the VLSI Journal10.1016/j.vlsi.2021.08.00881:C(342-353)Online publication date: 1-Nov-2021
      • (2018)PARMProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196090(1-6)Online publication date: 24-Jun-2018
      • (2017)IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing AlgorithmsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.267380825:7(2035-2044)Online publication date: 23-Jun-2017
      • (2014)Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming NetworksACM Transactions on Embedded Computing Systems10.1145/258466813:4s(1-25)Online publication date: 1-Apr-2014
      • (2013)Dynamic programming-based runtime thermal management (DPRTM)ACM Transactions on Design Automation of Electronic Systems10.1145/253438219:1(1-27)Online publication date: 20-Dec-2013
      • (2013)Hybrid wire‐surface wave interconnects for next‐generation networks‐on‐chipIET Computers & Digital Techniques10.1049/iet-cdt.2013.00307:6(294-303)Online publication date: Nov-2013
      • (2012)Surface wave communication system for on-chip and off-chip interconnectsProceedings of the Fifth International Workshop on Network on Chip Architectures10.1145/2401716.2401720(11-16)Online publication date: 1-Dec-2012

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