ABSTRACT
As verification activities dominate the systems development process efficient testbenches at an adequate level of abstraction are crucial factors to shorten time-to-market. We give an overview of the current state of ESL testbenches and the corresponding articles of the special session show advances and future directions of IEEE-1600-2011 SystemC in the context of testbenches for Transaction Level Modeling (TLM)[5][6][12][15][16].
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Index Terms
- Testbenches for advanced TLM verification
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