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A configurable test infrastructure using a mixed-language and mixed-level IP integration IP-XACT flow

Published: 07 October 2012 Publication History

Abstract

We present a reusable test infrastructure for RTL designs as an application of mixed-level and mixed-language integration using the IP-XACT standard. The test infrastructure is configurable, meaning that specific configurations can be generated from a template. The main part of the components in the test infrastructure is implemented using the SystemC TLM2 standard. A small part is implemented in VHDL. The design technology to generate configurations uses the IP-XACT standard. We present an application of the reusable test infrastructure for randomized IC verification. To this end, a specific test configuration is integrated with additional stubs and a DUT which are described in Verilog and VHDL. Software images are executed both on the test bench and the DUT. Our results demonstrate an efficient integration flow for mixed-language and mixed-level IPs through flow automation.

References

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ARM FastModels, http://www.arm.com/products/tools/models/fast-models.php
[2]
ARM Cortex Microcontroller Software Interface Standard, http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php
[3]
Cadence Incisive Enterprise Simulator, www.cadence.com/products/sd/enterprise_simulator
[4]
Carbon SOC Designer, http://www.carbondesignsystems.com/soc-designer-plus/
[5]
CoReUse 4.6, Hardware Verification Software Standard, http://www.ip-extreme.com/MediaFiles/ebooks/26.pdf
[6]
Esterel, http://www.esterel-technologies.com/
[7]
Magillem Design Services, http://www.magillem.com/eda/
[8]
Mentor HDL Designer, http://www.mentor.com/products/fpga/hdl_design/hdl_designer_series/
[9]
Mentor Vista, http://www.mentor.com/esl/vista/upload/vista-architect-ds.pdf
[10]
IP-XACT, Standard Structure for Packaging, Integratimg, and Reusing IP within Tool Flows, IEEE 1685--2009, http://standards.ieee.org/getieee/1685/download/1685--2009.pdf
[11]
SystemC Modeling Library, http://www.synopsys.com/cgi-bin/slcw/kits/reg.cgi
[12]
SystemC, Open SystemC Language Reference Manual, IEEE 1666--2011, http://standards.ieee.org/getieee/1666/download/1666--2011.pdf
[13]
SystemC TLM2, http://www.accellera.org/downloads/standards/systemc/tlm
[14]
Synopsys Core Assembler, http://www.synopsys.com/dw/ipdir.php?ds=core_assembler
[15]
Synopsys Virtualizer, http://www.synopsys.com/systems/virtualprototyping/Pages/default.aspx
[16]
Universal Verification Methodology, http://www.uvmworld.org/

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  1. A configurable test infrastructure using a mixed-language and mixed-level IP integration IP-XACT flow

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    cover image ACM Conferences
    CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
    October 2012
    596 pages
    ISBN:9781450314268
    DOI:10.1145/2380445
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 07 October 2012

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    Author Tags

    1. fastmodel
    2. ip-xact
    3. mixed-language
    4. mixed-level
    5. randomized verification
    6. rtl
    7. systemc
    8. tlm

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    ESWEEK'12
    ESWEEK'12: Eighth Embedded System Week
    October 7 - 12, 2012
    Tampere, Finland

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    CODES+ISSS '12 Paper Acceptance Rate 48 of 163 submissions, 29%;
    Overall Acceptance Rate 280 of 864 submissions, 32%

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