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From RTL IP to functional system-level models with extra-functional properties

Published: 07 October 2012 Publication History

Abstract

The paper presents a novel abstraction methodology for generating time- and power-annotated TLM models from synthesizable RTL descriptions. The proposed techniques allow the integration of existing RTL IP components into virtual platforms for early software development and platform design, configuration, and exploration. With the proposed approach, IP models can be natively integrated into SystemC TLM-2.0 platforms and executed 10-1000 times faster compared to state-of-the-art RTL simulators. The abstraction methodology guarantees preservation of the behaviour and timing of the RTL models. Target technology dependent power properties of IP components are represented as power state-machines and integrated into the abstracted TLM models. The experimental results show a relative error less than 10\% of the abstracted model's power consumption compared to state-of-the-art RTL power simulators. The evaluation has been performed on RTL IP components with different characteristics and demonstrates the effectiveness of the presented abstraction methodology.

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  • (2020)A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCsInternational Journal of Parallel Programming10.1007/s10766-020-00656-048:6(957-1007)Online publication date: 1-Dec-2020
  • (2018)Related WorkPower Estimation on Electronic System Level using Linear Power Models10.1007/978-3-030-01875-7_2(17-48)Online publication date: 15-Dec-2018
  • (2016)Empowering Mixed-Criticality System Engineers in the Dark Silicon Era: Towards Power and Temperature Analysis of Heterogeneous MPSoCs at System LevelModel-Implementation Fidelity in Cyber Physical System Design10.1007/978-3-319-47307-9_3(57-90)Online publication date: 10-Dec-2016
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  1. From RTL IP to functional system-level models with extra-functional properties

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      cover image ACM Conferences
      CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
      October 2012
      596 pages
      ISBN:9781450314268
      DOI:10.1145/2380445
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 07 October 2012

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      Author Tags

      1. hw/sw timing and power simulation
      2. rtl to tlm abstraction
      3. virtual prototypes

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      • Research-article

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      ESWEEK'12
      ESWEEK'12: Eighth Embedded System Week
      October 7 - 12, 2012
      Tampere, Finland

      Acceptance Rates

      CODES+ISSS '12 Paper Acceptance Rate 48 of 163 submissions, 29%;
      Overall Acceptance Rate 280 of 864 submissions, 32%

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      Cited By

      View all
      • (2020)A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCsInternational Journal of Parallel Programming10.1007/s10766-020-00656-048:6(957-1007)Online publication date: 1-Dec-2020
      • (2018)Related WorkPower Estimation on Electronic System Level using Linear Power Models10.1007/978-3-030-01875-7_2(17-48)Online publication date: 15-Dec-2018
      • (2016)Empowering Mixed-Criticality System Engineers in the Dark Silicon Era: Towards Power and Temperature Analysis of Heterogeneous MPSoCs at System LevelModel-Implementation Fidelity in Cyber Physical System Design10.1007/978-3-319-47307-9_3(57-90)Online publication date: 10-Dec-2016
      • (2015)Towards Satisfaction Checking of Power Contracts in UppaalLanguages, Design Methods, and Tools for Electronic System Design10.1007/978-3-319-24457-0_9(157-179)Online publication date: 12-Dec-2015
      • (2014)An ESL timing & power estimation and simulation framework for heterogeneous socs2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)10.1109/SAMOS.2014.6893210(181-190)Online publication date: Jul-2014
      • (2014)Powermonitor: a versatile API for automated power-aware ESL designProceedings of the 2014 Forum on Specification and Design Languages (FDL)10.1109/FDL.2014.7119350(1-4)Online publication date: Oct-2014
      • (2014)Multi-level modeling of wireless embedded systemsProceedings of the 2014 Forum on Specification and Design Languages (FDL)10.1109/FDL.2014.7119349(1-8)Online publication date: Oct-2014
      • (2014)Data-and State-Dependent Power Characterisation and Simulation of Black-Box RTL IP Components at System LevelProceedings of the 2014 17th Euromicro Conference on Digital System Design10.1109/DSD.2014.89(129-136)Online publication date: 27-Aug-2014
      • (2013)A database for the integration of power data on system levelEurocon 201310.1109/EUROCON.2013.6625009(361-368)Online publication date: Jul-2013
      • (2013)A Physical-Aware Abstraction Flow for Efficient Design-Space Exploration of a Wireless Body Area Network ApplicationProceedings of the 2013 Euromicro Conference on Digital System Design10.1109/DSD.2013.114(1005-1012)Online publication date: 4-Sep-2013
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