M. Langevin
Abstract
We present a fast recursive technique for estimating lower-bound performance of data path schedules. The method relies on the determination of an ASAPUC a(s Soon As Possible Under Constraint) time-step value for each node of the DFG (Data-Flow Graph) that is based on the ASAPUC values of its predecessor nodes. That is, the lower-bound estimation is applied to each subgraph permitting the derivation of a tight lower bound on the performance of the complete DFG. Applying the greedy lower-bound estimator of Rim and Jain [1994] to each subgraph improves the complete lower bound in more than 50% of the experiments reported in Rim and Jain [1994], and the CPU time is only about twice as long. The recursive methodology can be extended to exploit other lower-bound techniques, for example, considering other constraints such as the number of busses or registers.
- BENNOUR, I. AND ABOULHAMID, E. M. 1997. Lower-bounds on the iteration and initiation interval of functional pipelining and loop folding. Des. Autom. Embedded Syst. (to appear).Google Scholar
- CAMPOSANO, R. AND WILBERG, J. 1996. Embedded system design. Des. Autom. Embedded Syst. 1, 5-50. Google Scholar
- DEWILDE, P., DEPRETTERE, E., AND NOUTA, R. 1985. Parallel and pipelined VLSI implementation of signal processing algorithms. In VLSI and Modern Signal Processing, S. Y. Kung, H. J. Whitehouse, T. Kailath, Eds., Prentice-Hall, Englewood Cliffs, NJ.Google Scholar
- GAJSKI, D. D., VAHID, F., NARAYAN, S., AND GONG, J. 1994. Specification and Design of Embedded Systems. Prentice Hall, Englewood Cliffs, NJ. Google Scholar
- GAREY, M. R. AND JOHNSON, D.S. 1979. Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman, San Francisco. Google Scholar
- GEBOTYS, C. H. AND ELMASRY, M.I. 1991. Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis. In Proceedings of DAC (San Francisco, CA, June 17-21), 2-7. Google Scholar
- HWANG, C.-T., LEE, J.-H., AND HSU, Y.-C. 1991. A formal approach to the scheduling problem in high level synthesis. IEEE Trans. CAD 10, 464-475.Google Scholar
- HWANG, K. AND BRIGGS, F. A. 1986. Computer Architecture and Parallel Processing. McGraw-Hill, New York. Google Scholar
- JAIN, R., KUCUKCAKAR, K., MLINAR, M. J., AND PARKER, A. C. 1989. Experience with the ADAM synthesis system. In Proceedings of DAC (Las Vegas, NE, June 25-29), 56-61. Google Scholar
- LANGEVIN, M., CERNY, E., WILBERG, J., AND VIERHAUS, H.-T. 1995. Local microcode generation in system design. In Code Generation for Embedded Processors, P. Marwedel and G. Goossens, Eds., Kluwer Academic, Boston, MA, Ch. 10, 171-187.Google Scholar
- MCFARLAND, M. C., PARKER, A. C., AND CAMPOSANO, R. 1988. Tutorial on high-level synthesis. In Proceedings of DAC (Anaheim, CA, June 12-15), 330-336. Google Scholar
- PAPACHRISTOU, C. A. AND KONUK, H. 1989. A high-level synthesis technique based on linear programming. Tech. Rep., Computer Engineering and Science Dept., Case Western Reserve Univ., Nov.Google Scholar
- PARK, N. AND PARKER, A.C. 1988. Sehwa: A software package for synthesis of pipelines from behavioral specifications. IEEE Trans. CAD 7, 356-370.Google Scholar
- PAULIN, P. G. AND KNIGHT, J.P. 1989. Force-directed scheduling for the behavioral synthesis of ASIC's. IEEE Trans. CAD 8, 661-679.Google Scholar
- RABAEY, g. M. AND POTKONJAK, M. 1994. Estimating implementation bounds for real time DSP application specific circuits. IEEE Trans. CAD 13, 669-683.Google Scholar
- RIM, M. AND JAIN, R. 1994. Lower-bound performance estimation for high-level synthesis scheduling problem. IEEE Trans. CAD 13, 451-458.Google Scholar
- SHARMA, A. AND JAIN, R. 1993. Estimating architectural resources and performance for high-level synthesis applications. IEEE Trans. VLSI Syst. 1.Google Scholar
- TIMMER, A. H. AND JESS, g. A. G. 1993. Execution interval analysis under resource constraints. In Proceedings of ICCAD (Santa Clara, CA, Nov. 7-11), 454-459. Google Scholar
Index Terms
- A recursive technique for computing lower-bound performance of schedules
Recommendations
Lower and Upper Bounds on Time for Multiprocessor Optimal Schedules
The lower and upper bounds on the minimum time needed to process a given directedacyclic task graph for a given number of processors are derived. It is proved that theproposed lower bound on time is not only sharper than the previously known values ...
Dense open-shop schedules with release times
We study open-shop scheduling problems with job release times. The objective is to minimize the makespan. Dense schedules, easy to construct, are often used as approximate solutions. Performance ratios of the makespans from dense schedules and that of ...
An optimal lower bound for anonymous scheduling mechanisms
EC '09: Proceedings of the 10th ACM conference on Electronic commerceWe consider the problem of designing truthful mechanisms to minimize the makespan on m unrelated machines. In their seminal paper, Nisan and Ronen [14] showed a lower bound of 2, and an upper bound of m, thus leaving a large gap. They conjectured that ...
Reviews
Vladimir Botchev
A recursive technique for estimating lower-bound performance of data path schedules is presented. The technique gives an improved complete lower bound in many cases where the Rim and Jain estimator was employed. In the introduction, the authors focus on estimating lower-bound performance of schedules under resource constraints for acyclic finite dataflow graphs. In the next section, they consider the relaxation of the scheduling problem, using the Rim and Jain framework to introduce concepts. At the end of this section, the authors formulate the key points to improve on. Section 3 contains the new algorithm for computing ASAPUC values (“as soon as possible under constraints” time for each operation). The last section before the conclusion gives a huge body of experimental results, mainly drawn from digital signal processing. This section is of interest to a broad range of professionals because, as the authors state in the conclusion, similar considerations may apply to software schedules. In the light of existing and forthcoming very high speed digital signal processors (including the TMS320C6xx), where scheduling of instructions among available processing units emerges as a major issue, this work should be enlightening to many people who do not have much knowledge of this area.
Access critical reviews of Computing literature here
Become a reviewer for Computing Reviews.
Comments