skip to main content
research-article

A self-tuning design methodology for power-efficient multi-core systems

Published: 16 January 2013 Publication History

Abstract

This article aims to achieve computational reliability and energy efficiency through codevelopment of algorithms, device, and circuit designs for application-specific, reconfigurable architectures. The new methodology characterizes aging-switching activity and aging-supply voltage relationships that are applicable for minimizing power consumption and task execution efficiency in order to achieve low bit energy ratio (BER). In addition, a new dynamic management algorithm (DMA) is proposed to alleviate device degradation and to extend system lifespan. In contrast to traditional workload balancing schemes in which cores are regarded as homogeneous, the new algorithm ranks cores as “highly competitive,” “less competitive,” and “not competitive” according to their various competitiveness. Core competitiveness is evaluated based upon their reliability, temperature, and timing requirements. Consequently, “competitive” cores will take charge of the majority of the tasks at relatively high voltage/frequency without violating power and timing budgets, while “not competitive” cores will have light workloads to ensure their reliability. The new approach combines intrinsic device characteristics (aging-switching activity and aging-supply voltage curves) into an integrated framework to achieve high reliability and low energy level with graceful degradation of system performance. Experimental results show that the proposed method has achieved up to 20% power reduction, with about 4% performance degradation (in terms of accomplished workload and system throughput), compared with traditional workload balancing methods. The new method also improves system mean-time-to-failure (MTTF) by up to 25%.

References

[1]
Bhardwaj, S., Wang, W., Vttikonda, R., Cao, Y., and Vrudhula, S. 2006. Predictive modeling of the nbti effect for reliable design. In Proceedings of the Custom Integrated Circuits Conference (CICC'06). 189--192.
[2]
Chen, G., Chuah, K. Y., Li, M. F., Chan, D. S., Ang, C. H., Zheng, J. Z., Jin, Y., and Kwong, D. L. 2003. Dynamic nbti of pmos transistors and its impact on device lifetime. In Proceedings of the International Reliability Physics Symposium (IRPS'03). 196--202.
[3]
Chen, M., Reddy, V., Carulli, J., Krishnan, S., Srinivasan, V., Rentala, V., and Cao, Y. 2011. A tdc-based test platform for dynamic circuit aging characterization. In Proceedings of the International Reliability Physics Symposium (IRPS'11). 2.B.2.1--2.B.2.5.
[4]
Coskun, A. K., Rosing, T. S., and Whisnan, K. 2007. Temperature aware task scheduling in mpsocs. In Proceedings of the Design, Automation, and Test in Europe (DATE'07). 1--6.
[5]
Green, P. and Wang, J. M. 2009. A new nbti sensor for chip multi-processor (cmp) monitoring applications. In Proceedings of the Austin Conference on Circuit and Systems.
[6]
Greskamp, B., Sarangi, S. R., and Torrellas, J. 2007. Threshold voltage variation effects on aging-related hard failure rates. In Proceedings of the International Symposium on Circuits and Systems (ISCAS'07). 1261--1264.
[7]
Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T., and Brown, R. B. 2001. Mibench: A free, commercially representative embedded benchmark suite. In Proceedings of the International Workshop on Workload Characterization. 3--14.
[8]
Ho, Y. C. 1997. On the numerical solutions of stochastic optimization problem. IEEE Trans. Autom. Control 42, 5, 727--729.
[9]
Ho, Y. C. 1999. An explanation of ordinal optimization: Soft computing for hard problems. J. Inform. Sci. 113, 3, 169--192.
[10]
Hung, W.-L., Xie, Y., Vijaykrishnan, N., Kandemir, M., and Irwin, M. J. 2005. Thermal-aware task allocation and scheduling for embedded systems. In Proceedings of the Design, Automation, and Test in Europe (DATE'05). 898--899.
[11]
Kahng, A. B., Kang, S., Kumar, R., and Sartori, J. 2010a. Designing a processor from the ground up to allow voltage/reliability tradeoffs. In Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA'10). 1--11.
[12]
Kahng, A. B., Kang, S., Kumar, R., and Sartori, J. 2010b. Slack redistribution for graceful degradation under voltage overscaling. In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC'10). 825--831.
[13]
Karl, E., Singh, P., Blaauw, D., and Sylvester, D. 2008. Compact in-situ sensors for monitoring negative-bias-temperature-instability effect and oxide degradation. In Proceedings of the International Solid-State Conference (ISSCC'08). 410--623.
[14]
Lee, C., Potkonjak, M., and Mangione-Smith, W. H. 2008. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the International Symposium on Microarchitecture (MICRO'08). 330--335.
[15]
Lee, E. A. and Messerschmitt, D. G. 1987. Synchronous data flow. Proc. IEEE 75, 9, 1235--1245.
[16]
Lin, S.-C. and Banerjee, K. 2008. Cool chips: Opportunities and implications for power and thermal management. IEEE Trans. Electron Devices 55, 1, 245--255.
[17]
Mahapatra, S., Kumar, P. B., and Alam, M. A. 2004. Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-mosfets. IEEE Trans. Electron Devices 51, 9, 1371--1379.
[18]
Memik, G., Mangione-Smith, W. H., and Hu, W. 2001. Netbench: A benchmarking suite for network processors. In Proceedings of the International Conference on Computer-Aided Design (ICCAD'08). 39--42.
[19]
Narayanan, S., Lyle, G., Kumar, R., and Jones, D. 2009. Testing the critical operating point (cop) hypothesis using fpga emulation of timing errors in over-scaled soft-processors. In Proceedings of the SELSE 5 Workshop - Silicon Errors in Logic-System Effects.
[20]
Padilla, A., Yeung, C. W., Shin, C., Cho, M. H., Hu, C., and Liu, T. K. 2008. Feedback fet: A novel transistor exhibiting steep switching behavior at low bias voltages. In Proceedings of the International Electron Devices Meeting (IEDM'08). 1--4.
[21]
Rabaey, J. 2007. Low Power Design Essentials. Springer, New York, NY.
[22]
Reddy, V., Krishnan, A. T., Marshall, A., Rodriguez, J., Natarajan, S., Rost, T., and Krishnan, S. 2002. Impact of negative bias temperature instability of digital circuit reliability. In Proceedings of the International Reliability Physics Symposium (IRPS'02). 248--254.
[23]
Skadron, K., Stan, M. R., Sankaranarayanan, K., Huang, W., Velusamy, S., and Tarjan, D. 2004. Temperature-aware microarchitecture: modeling and implementation. ACM Trans. Archit. Code Optim. 1, 1, 94--125.
[24]
Srinivasan, J., Adve, S. V., Bose, P., and Rivers, J. A. 2004. The impact of technology scaling on lifetime reliability. In Proceedings of the Dependable Systems and Networks. 177--186.
[25]
Srinivasan, J., Adve, S. V., Bose, P., and Rivers, J. A. 2005. Exploiting structural duplication for lifetime reliability enhancement. In Proceedings of the International Symposium on Computer Architecture (ISCA'05). 520--531.
[26]
Sun, J., Lysecky, R., Shankar, K., Kodi, A., Louri, A., and Wang, J. M. 2010. Workload capacity considering nbti degradation in multi-core systems. In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC'10). 450--455.
[27]
Vattikonda, R., Wang, W., and Cao, Y. 2006. Modeling and minimization of pmos nbti effect for robust nanometer design. In Proceedings of the Design Automation Conference (DAC'06). 1047--1052.
[28]
Waldshmidt, K., Haase, J., Hofmann, A., Damm, M., and Hauser, D. 2006. Reliability-aware power management of multi-core systems (mpsocs). In Proceedings of the Dynamically Reconfigurable Architectures. 520--531.
[29]
Wang, W., Reddy, V., Krishnan, A. T., Vattikonda, R., Krishnan, S., and Cao, Y. 2007. Compact modeling and simulation of circuit reliability for 65nm cmos technology. IEEE Trans. Device Mater. Reliab. 7, 4, 509--517.
[30]
Wang, W., Yang, S., Bhardwaj, S., Vrudhula, S., Liu, F., and Cao, Y. 2010. The impact of nbti effect on combinational circuit: modeling, simulation, and analysis. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 18, 2, 173--183.
[31]
Zheng, R., Velamala, J., Reddy, V., Balakrishnan, V., Mintarno, E., Mitra, S., Krishnan, S., and Cao, Y. 2009. Circuit aging prediction for low-power operation. In Proceedings of the Custom Integrated Circuits Conference (CICC'09). 427--430.

Cited By

View all
  • (2025)Reliability analysis of the intricacies of interfacial trap charges in HD-VS-FeFinFET and its applicability as CMOS inverterMicroelectronics Reliability10.1016/j.microrel.2025.115610166(115610)Online publication date: Mar-2025
  • (2021)Recent Developments in Parallel and Distributed Computing for Remotely Sensed Big Data ProcessingProceedings of the IEEE10.1109/JPROC.2021.3087029(1-24)Online publication date: 2021
  • (2019)Aging-Aware Workload Management on Embedded GPU Under Process VariationIEEE Transactions on Computers10.1109/TC.2018.278990467:7(920-933)Online publication date: 3-Jan-2019
  • Show More Cited By

Index Terms

  1. A self-tuning design methodology for power-efficient multi-core systems

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 18, Issue 1
    Special section on adaptive power management for energy and temperature-aware computing systems
    January 2013
    319 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/2390191
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Journal Family

    Publication History

    Published: 16 January 2013
    Accepted: 01 September 2012
    Revised: 01 July 2012
    Received: 01 March 2012
    Published in TODAES Volume 18, Issue 1

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. Multi-core systems
    2. competitive index
    3. dynamic management algorithm
    4. negative bias temperature instability
    5. self-tuning design

    Qualifiers

    • Research-article
    • Research
    • Refereed

    Funding Sources

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)3
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 18 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2025)Reliability analysis of the intricacies of interfacial trap charges in HD-VS-FeFinFET and its applicability as CMOS inverterMicroelectronics Reliability10.1016/j.microrel.2025.115610166(115610)Online publication date: Mar-2025
    • (2021)Recent Developments in Parallel and Distributed Computing for Remotely Sensed Big Data ProcessingProceedings of the IEEE10.1109/JPROC.2021.3087029(1-24)Online publication date: 2021
    • (2019)Aging-Aware Workload Management on Embedded GPU Under Process VariationIEEE Transactions on Computers10.1109/TC.2018.278990467:7(920-933)Online publication date: 3-Jan-2019
    • (2019)ROAD: Improving Reliability of Multi-core System via Asymmetric Aging2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD45719.2019.8942178(1-8)Online publication date: Nov-2019
    • (2019)Hierarchy of Smart Awareness in Assembly 4.0 SystemsIFAC-PapersOnLine10.1016/j.ifacol.2019.11.41352:13(1508-1512)Online publication date: 2019
    • (2017)Low-overhead Aging-aware Resource Management on Embedded GPUsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062277(1-6)Online publication date: 18-Jun-2017
    • (2016)Toward Smart Embedded SystemsACM Transactions on Embedded Computing Systems10.1145/287293615:2(1-27)Online publication date: 17-Feb-2016
    • (2016)eCope: Workload-Aware Elastic Customization for Power Efficiency of High-End ServersIEEE Transactions on Cloud Computing10.1109/TCC.2015.24648024:2(237-249)Online publication date: 1-Apr-2016

    View Options

    Login options

    Full Access

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media