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Verification work reduction methodology in low-power chip implementation

Published: 16 January 2013 Publication History

Abstract

In order to achieve satisfactory verification for complicated low-power demands in green products, we propose a verification work reduction methodology. It consists of three step, namely virtual, direct actual, and actual model simulations. Virtual low-power simulation inserts low-power cells, such as isolators or level shifters, virtually and simulates logical behavior for design under test (DUT) based on user-defined power mode. Direct actual low-power simulation replaces behavior models without non-logical pins for some of modules with actual models with non-logical pins, which are Vdd and Gnd, and simulates DUT in mixed level. Actual low-power simulation simulates DUT by using actual models with non-logical pins for all cells and hard macros. We introduce techniques which classify the type of the bugs on which we focus at each verification step and prevent the concerned bugs from leaking to the latter verification step as much as possible.
We applied our methodology to an actual chip and could reduce the total simulation period until tape-out by 38.8% and the total chip development period by 10%, compared with the conventional methodology.

References

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Chen, S. H. and Lin, J. Y. 2008. Experiences of low power design implementation and verification, In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC'08). 742--747.
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  1. Verification work reduction methodology in low-power chip implementation

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    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 18, Issue 1
    Special section on adaptive power management for energy and temperature-aware computing systems
    January 2013
    319 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/2390191
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 16 January 2013
    Accepted: 01 July 2012
    Revised: 01 November 2011
    Received: 01 July 2011
    Published in TODAES Volume 18, Issue 1

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    Author Tags

    1. Low power
    2. logic simulation
    3. power intent
    4. power shutdown
    5. verification efficiency

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