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A new high radix-2r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers

Published: 05 December 2012 Publication History

Abstract

This paper addresses the problem of multiplication with large operand sizes (N≥32). We propose a new recursive recoding algorithm that shortens the critical path of the multiplier and reduces the hardware complexity of partial-product-generators as well. The new recoding algorithm provides an optimal space/time partitioning of the multiplier architecture for any size N of the operands. As a result, the critical path is drastically reduced to 33√ N / 2 -- 3 with no area overhead in comparison to modified Booth algorithm that shows a critical path of N/2 in adder stages. For instance, only 7 adder stages are needed for a 64-bit two's complement multiplier. Confronted to reference algorithms for N=64, important gain ratios of 1.62, 1.71, 2.64 are obtained in terms of multiply-time, energy consumption per multiplyoperation, and total gate count, respectively.

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Published In

cover image ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News  Volume 40, Issue 4
September 2012
48 pages
ISSN:0163-5964
DOI:10.1145/2411116
Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 December 2012
Published in SIGARCH Volume 40, Issue 4

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Author Tags

  1. high-radix multiplication
  2. low-power multiplication
  3. multibit recoding multiplication
  4. partial product generator (PPG)
  5. register-transfer-level (RTL)

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