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Comparing software and hardware schemes for reducing the cost of branches
Special Issue: Proceedings of the 16th annual international symposium on Computer ArchitecturePipelining has become a common technique to increase throughput of the instruction fetch, instruction decode, and instruction execution portions of modern computers. Branch instructions disrupt the flow of instructions through the pipeline, increasing ...
Comparing software and hardware schemes for reducing the cost of branches
ISCA '89: Proceedings of the 16th annual international symposium on Computer architecturePipelining has become a common technique to increase throughput of the instruction fetch, instruction decode, and instruction execution portions of modern computers. Branch instructions disrupt the flow of instructions through the pipeline, increasing ...
Software and hardware techniques to optimize register file utilization in VLIW architectures
High-performance microprocessors are currently designed with the purpose of exploiting instruction level parallelism (ILP). The techniques used in their design and the aggressive scheduling techniques used to exploit this ILP tend to increase the ...
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