S. Ramprasath
ABSTRACT
Due to the statistical nature of gate delays in current day technologies, measures such as path criticality and node/edge criticality are required for timing optimization. Node criticalities are usually computed using the complementary path delay. In order to speed up computations, it has been recently proposed that the circuit delay be used instead. In this paper, we show that there is a monotonic relationship between the node criticalities computed using the circuit delay and the complementary delay. They are not equal, but they can be used interchangeably. We discuss the sources of error in this computation and propose methods for more accurate computations. We also introduce a measure that is very easy to compute and is an approximate indicator of criticality. Since it is easy to compute, it can also be used effectively for pruning the number of edges involved in criticality computations thus improving the speed of criticality computations. The speedup obtained can be as large as an order of magnitude for some of larger circuits in the ISCAS benchmarks.
- C. Visweswariah, K. Ravindran, K. Kalafala, S. Walker, and S. Narayan, "First-order incremental block-based statistical timing analysis," in Proc. DAC, 2004, pp. 331--336. Google Scholar
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- J. Xiong, V. Zolotov, N. Venkateswaran, and C. Visweswariah, "Criticality computation in parameterized statistical timing," in Proc. DAC, 2006, pp. 63--68. Google ScholarDigital Library
- H. Mogal, H. Qian, S. Sapatnekar, and K. Bazargan, "Fast and accurate statistical criticality computation under process variations," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 28, no. 3, pp. 350--363, March 2009. Google ScholarDigital Library
- X. Li, J. Le, M. Celik, and L. Pileggi, "Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 6, pp. 1041--1054, June 2008. Google ScholarDigital Library
- A. Agarwal, K. Chopra, and D. Blaauw, "Statistical timing based optimization using gate sizing," in Proc. DATE, 2005, pp. 400--405. Google ScholarDigital Library
- J. Xiong, V. Zolotov, and C. Visweswariah, "Incremental criticality and yield gradients," in Proc. DATE, 2008, pp. 1130--1135. Google ScholarDigital Library
- J. Chung, J. Xiong, V. Zolotov, and J. A. Abraham, "Path criticality computation in parameterized statistical timing analysis using a novel operator," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 31, no. 4, pp. 497--508, 2012.Google ScholarDigital Library
- A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda, "Statistical delay computation considering spatial correlations," in Proc. ASP-DAC, 2003, pp. 271--276. Google ScholarDigital Library
- H. Chang and S. Sapatnekar, "Statistical timing analysis under spatial correlations," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 9, pp. 1467--1482, sept. 2005. Google ScholarDigital Library
- C. E. Clark, "The greatest of a finite set of random variables," OPERATIONS RESEARCH, vol. 9, no. 2, pp. 145--162, 1961.Google ScholarDigital Library
- D. Sinha, H. Zhou, and N. Shenoy, "Advances in computation of the maximum of a set of gaussian random variables," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 8, pp. 1522--1533, Aug. 2007. Google ScholarDigital Library
- D. Blaauw, K. Chopra, A. Srivastava, and L. Scheffer, "Statistical timing analysis: From basic principles to state of the art," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 4, pp. 589--607, April 2008. Google ScholarDigital Library
- F. Wane, Y. Xie, and H. Ju, "A novel criticality computation method in statistical timing analysis," in Proc. DATE, 2007, pp. 1--6. Google ScholarDigital Library
- Y. Zhan, A. Strojwas, M. Sharma, and D. Newmark, "Statistical critical path analysis considering correlations," in Proc. ICCAD, 2005, pp. 699--704. Google ScholarDigital Library
- J. Chung, J. Xiong, V. Zolotov, and J. Abraham, "Path criticality computation in parameterized statistical timing analysis," in Proc. ASP-DAC, 2011, pp. 249--254. Google ScholarDigital Library
Index Terms
- On the computation of criticality in statistical timing analysis
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