Sebastian Steinhorst
Lars Hedrich
ABSTRACT
In this paper a novel approach to discrete state space modeling of nonlinear analog circuits is presented, based on the introduction of an underlying discrete analog transition structure (DATS) and the related optimization problem of accurately representing a nonlinear analog circuit with a DATS. Starting from a circuit netlist, a partitioning of the state space to the discrete model is generated parallel and orthogonal to the trajectories of the state space dynamics. Therefore, compared to previous approaches, a significantly higher accuracy of the model is achieved with a lower number of states. The mapping of the partitioning to a DATS enables the application of formal verification algorithms. Experimental validations show the soundness of the approach with an increase in accuracy between a factor of 4 to 10 compared to the state of the art. A model checking case study illustrates the application of the new discretization algorithm to identify a hidden circuit design error.
- R. P. Kurshan and K. L. McMillan. Analysis of digital circuits through symbolic reduction. IEEE Trans. on CAD of Integrated Circuits and Systems, 10(11): 1356--1371, 1991. Google Scholar
Digital Library
- T. R. Dastidar and P. P. Chakrabarti. A verification system for transient response of analog circuits. ACM Trans. Des. Autom. Electron. Syst., 12(3): 1--39, 2007. Google ScholarDigital Library
- D. Walter, S. Little, C. Myers, N. Seegmiller, and T. Yoneda. Verification of analog/mixed-signal circuits using symbolic methods. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(12): 2223--2235, 2008. Google ScholarDigital Library
- C. Gu and J. Roychowdhury. FSM model abstraction for analog/mixed-signal circuits by learning from I/O trajectories. In Proc. of the 16th Asia and South Pacific Design Automation Conference, ASPDAC '11, pages 7--12, 2011. Google ScholarDigital Library
- W. Hartong, L. Hedrich, and E. Barke. Model checking algorithms for analog verification. In Proc. of the 39th conference on Design automation (DAC '02), pages 542--547, 2002. Google ScholarDigital Library
- S. Steinhorst and L. Hedrich. Model Checking of Analog Systems using an Analog Specification Language. In Proc. of the Conference on Design, Automation and Test in Europe 2008 (DATE'08), pages 324--329, 2008. Google ScholarDigital Library
- T. Dang, A. Donzé, and O. Maler. Verification of analog and mixed-signal circuits using hybrid system techniques. In A. J. Hu and A. K. Martin, editors, FMCAD, volume 3312 of Lecture Notes in Computer Science, pages 21--36. Springer, 2004.Google Scholar
- M. Althoff, A. Rajhans, B. H. Krogh, S. Yaldiz, X. Li, and L. Pileggi. Formal verification of digital phase-locked loops using reachability analysis and continuization. In ICCAD '11: Proc. of the 2011 International Conference on Computer-Aided Design, pages 659--666, 2011. Google ScholarDigital Library
- D. E. Schwarz and C. Tischendorf. Structural analysis of electric circuits and consequences for MNA. Int. Journal of Circuit Theory and Applications, 28(2): 131--162, 2000.Google ScholarCross Ref
- E. M. Clarke, O. Grumberg, and D. A. Peled. Model checking. Springer, 1999. Google ScholarDigital Library
- G. H. Golub and C. F. Van Loan. Matrix computations. Johns Hopkins Univ Pr, 1996.Google Scholar
- A. Vladimirescu. The SPICE book. John Wiley & Sons, Inc. New York, NY, USA, 1994. Google ScholarDigital Library
- J. L. Bentley. K-d trees for semidynamic point sets. In SCG '90: Proceedings of the sixth annual symposium on Computational geometry, pages 187--197, New York, NY, USA, 1990. ACM. Google ScholarDigital Library
- K. D. Jones, J. Kim, and V. Konrad. Some 'real world' problems in the analog and mixed signal domains. In G. J. Pace and S. Singh, editors, Seventh International Workshop on Designing Correct Circuits, Budapest, pages 15--29. ETAPS 2008, March 2008.Google Scholar
Index Terms
- Trajectory-directed discrete state space modeling for formal verification of nonlinear analog circuits
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