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Voltage-aware chip-level design for reliability-driven pin-constrained EWOD chips

Published: 05 November 2012 Publication History

Abstract

Electrowetting-on-dielectric (EWOD) chips have become the most promising technology to realize pin-constrained digital microfluidic biochips (PDMFBs). In the design flow of EWOD chips, reliability is a critical challenge as it directly affects execution of bioassays. The major factor to degrade chip reliability is the trapped charge problem, which is induced by excessive applied voltage. Nevertheless, to comply with the pin constraint for PDMFBs, signal merging is inevitably involved, and thereby incurring trapped charges due to unawareness of applied voltage. Except for the trapped charge problem, wire routing to accomplish electrical connections increases the design complexity of pin-constrained EWOD chips. Unfortunately, no existing works tackle the problems of excessive applied voltage and wire routing, and thus the resultant chip will have more probabilities to fail during execution or can not be realized because of wire routing problem. In this paper, we present a network-flow based algorithm for reliability-driven pin-constrained EWOD chips with the consideration of voltage issue. Our algorithm not only minimizes the reliability problem induced by signal merging but also provides a comprehensive routing solution for EWOD chip-level designs. The experimental results demonstrate the effectiveness of proposed algorithm on real-life chips.

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cover image ACM Conferences
ICCAD '12: Proceedings of the International Conference on Computer-Aided Design
November 2012
781 pages
ISBN:9781450315739
DOI:10.1145/2429384
  • General Chair:
  • Alan J. Hu
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 November 2012

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  • (2020)Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic BiochipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.289482039:3(613-625)Online publication date: Mar-2020
  • (2019)Harnessing the Granularity of Micro-Electrode-Dot-Array Architectures for Optimizing Droplet Routing in BiochipsACM Transactions on Design Automation of Electronic Systems10.1145/336599325:1(1-37)Online publication date: 4-Dec-2019
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  • (2017)Adaptation of Biochemical Protocols to Handle Technology-Change for Digital MicrofluidicsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258562236:3(370-383)Online publication date: 1-Mar-2017
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  • (2015)SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD ChipsProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717777(49-56)Online publication date: 29-Mar-2015
  • (2015)Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic BiochipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.238782834:4(529-539)Online publication date: Apr-2015
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