research-article

Distributed memory interface synthesis for network-on-chips with 3D-stacked DRAMs

Authors:

Jian-Jia ChenAuthors Info & Claims

ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

Pages 458 - 465

https://doi.org/10.1145/2429384.2429479

Published: 05 November 2012 Publication History

Abstract

Stacking DRAMs on processing cores by Through-Silicon Vias (TSVs) provides abundant bandwidth and enables a distributed memory interface design. To achieve the best balance in performance and cost in an application-specific system, the distributed memory interface should be tailored for the target applications. In this paper, we propose the first distributed memory interface synthesis framework for application-specific Network-on-Chips (NoCs) with 3D-stacked DRAMs. To maximize the performance of a selected hardware configuration, the proposed framework co-synthesizes the hardware configuration of the distributed memory interface, and the software configuration, e.g. task mapping and data assignment. Since TSVs have adverse impact on chip costs and yields, the goal of the framework is minimizing the number of TSVs provided that the user-defined performance constraint is met.

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Cited By

Liu CChen YHariyama MHung CCerny TShin DBechini A(2020)Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memoriesProceedings of the 35th Annual ACM Symposium on Applied Computing10.1145/3341105.3373858(546-553)Online publication date: 30-Mar-2020
https://dl.acm.org/doi/10.1145/3341105.3373858
Liu CWu CChen YHung CSaid L(2018)Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memoriesProceedings of the 2018 Conference on Research in Adaptive and Convergent Systems10.1145/3264746.3264771(243-248)Online publication date: 9-Oct-2018
https://dl.acm.org/doi/10.1145/3264746.3264771
Ro YCho HLee EJung DSon YAhn JLee J(2017)SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2017.31(517-528)Online publication date: Feb-2017
https://doi.org/10.1109/HPCA.2017.31
Show More Cited By

Index Terms

Distributed memory interface synthesis for network-on-chips with 3D-stacked DRAMs

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Published In

cover image ACM Conferences

ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

November 2012

781 pages

ISBN:9781450315739

DOI:10.1145/2429384

General Chair:
Alan J. Hu
Univ. of British Columbia, Vancouver, BC, Canada

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IEEE CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2012

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Research-article

Funding Sources

National Science Council Taiwan
Excellent Research Projects of National Taiwan University
Industry Technology Research Institute
Etron Technology Inc.

Conference

ICCAD '12

Sponsor:

SIGDA

ICCAD '12: The International Conference on Computer-Aided Design

November 5 - 8, 2012

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Liu CChen YHariyama MHung CCerny TShin DBechini A(2020)Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memoriesProceedings of the 35th Annual ACM Symposium on Applied Computing10.1145/3341105.3373858(546-553)Online publication date: 30-Mar-2020
https://dl.acm.org/doi/10.1145/3341105.3373858
Liu CWu CChen YHung CSaid L(2018)Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memoriesProceedings of the 2018 Conference on Research in Adaptive and Convergent Systems10.1145/3264746.3264771(243-248)Online publication date: 9-Oct-2018
https://dl.acm.org/doi/10.1145/3264746.3264771
Ro YCho HLee EJung DSon YAhn JLee J(2017)SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2017.31(517-528)Online publication date: Feb-2017
https://doi.org/10.1109/HPCA.2017.31
Ge FZhan JXie YNarayanan V(2015)Exploring memory controller configurations for many-core systems with 3D stacked DRAMsSixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085489(565-570)Online publication date: Mar-2015
https://doi.org/10.1109/ISQED.2015.7085489
Schonberger AHofmann K(2014)3DMemory — Memory usage analysis tool2014 3rd Mediterranean Conference on Embedded Computing (MECO)10.1109/MECO.2014.6862663(81-85)Online publication date: Jun-2014
https://doi.org/10.1109/MECO.2014.6862663

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